git.sur5r.net Git - u-boot/blob - include/configs/PM828.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #undef CONFIG_SYS_RAMBOOT
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_PM828            1       /* ...on a PM828 module */
  23 #define CONFIG_CPM2             1       /* Has a CPM2 */
  24
  25 #ifndef CONFIG_SYS_TEXT_BASE
  26 #define CONFIG_SYS_TEXT_BASE    0x40000000      /* Standard: boot 64-bit flash */
  27 #endif
  28
  29 #undef CONFIG_DB_CR826_J30x_ON          /* J30x jumpers on D.B. carrier */
  30
  31 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  32
  33 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  34
  35 #undef  CONFIG_BOOTARGS
  36 #define CONFIG_BOOTCOMMAND                                                      \
  37         "bootp;"                                                                \
  38         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  39         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
  40         "bootm"
  41
  42 /* enable I2C and select the hardware/software driver */
  43 #define CONFIG_SYS_I2C
  44 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
  45 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
  46 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
  47 /*
  48  * Software (bit-bang) I2C driver configuration
  49  */
  50 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
  51 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
  52 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
  53 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
  54 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
  55                         else    iop->pdat &= ~0x00010000
  56 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
  57                         else    iop->pdat &= ~0x00020000
  58 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  59
  60
  61 #define CONFIG_RTC_PCF8563
  62 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  63
  64 /*
  65  * select serial console configuration
  66  *
  67  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  68  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  69  * for SCC).
  70  *
  71  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  72  * defined elsewhere (for example, on the cogent platform, there are serial
  73  * ports on the motherboard which are used for the serial console - see
  74  * cogent/cma101/serial.[ch]).
  75  */
  76 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
  77 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
  78 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  79 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
  80
  81 /*
  82  * select ethernet configuration
  83  *
  84  * if CONFIG_ETHER_ON_SCC is selected, then
  85  *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
  86  *
  87  * if CONFIG_ETHER_ON_FCC is selected, then
  88  *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
  89  *
  90  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  91  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  92  */
  93 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  94
  95 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  96 #define CONFIG_ETHER_INDEX    1         /* which SCC channel for ethernet */
  97
  98 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  99 /*
 100  * - Rx-CLK is CLK11
 101  * - Tx-CLK is CLK10
 102  */
 103 #define CONFIG_ETHER_ON_FCC1
 104 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
 105 #ifndef CONFIG_DB_CR826_J30x_ON
 106 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
 107 #else
 108 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
 109 #endif
 110 /*
 111  * - Rx-CLK is CLK15
 112  * - Tx-CLK is CLK14
 113  */
 114 #define CONFIG_ETHER_ON_FCC2
 115 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 116 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 117 /*
 118  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 119  * - Enable Full Duplex in FSMR
 120  */
 121 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 122 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 123
 124 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 125 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 126
 127 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
 128 #define CONFIG_BAUDRATE         230400
 129 #else
 130 #define CONFIG_BAUDRATE         9600
 131 #endif
 132
 133 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 134 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 135
 136 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 137
 138 /*
 139  * BOOTP options
 140  */
 141 #define CONFIG_BOOTP_SUBNETMASK
 142 #define CONFIG_BOOTP_GATEWAY
 143 #define CONFIG_BOOTP_HOSTNAME
 144 #define CONFIG_BOOTP_BOOTPATH
 145 #define CONFIG_BOOTP_BOOTFILESIZE
 146
 147
 148 /*
 149  * Command line configuration.
 150  */
 151 #include <config_cmd_default.h>
 152
 153 #define CONFIG_CMD_BEDBUG
 154 #define CONFIG_CMD_DATE
 155 #define CONFIG_CMD_DHCP
 156 #define CONFIG_CMD_EEPROM
 157 #define CONFIG_CMD_I2C
 158 #define CONFIG_CMD_NFS
 159 #define CONFIG_CMD_SNTP
 160
 161 #ifdef CONFIG_PCI
 162 #define CONFIG_PCI_INDIRECT_BRIDGE
 163 #define CONFIG_CMD_PCI
 164 #endif
 165
 166 /*
 167  * Miscellaneous configurable options
 168  */
 169 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 170 #if defined(CONFIG_CMD_KGDB)
 171 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 172 #else
 173 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 174 #endif
 175 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 176 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 177 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 178
 179 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 180 #define CONFIG_SYS_MEMTEST_END 0x0C00000        /* 4 ... 12 MB in DRAM  */
 181
 182 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 183
 184 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address                */
 185
 186 /*
 187  * For booting Linux, the board info and command line data
 188  * have to be in the first 8 MB of memory, since this is
 189  * the maximum mapped by the Linux kernel during initialization.
 190  */
 191 #define CONFIG_SYS_BOOTMAPSZ         (8 << 20)       /* Initial Memory map for Linux */
 192
 193 /*-----------------------------------------------------------------------
 194  * Flash and Boot ROM mapping
 195  */
 196
 197 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 198 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 199 #define CONFIG_SYS_FLASH0_BASE          0x40000000
 200 #define CONFIG_SYS_FLASH0_SIZE          0x02000000
 201 #define CONFIG_SYS_DOC_BASE             0xFF800000
 202 #define CONFIG_SYS_DOC_SIZE             0x00100000
 203
 204
 205 /* Flash bank size (for preliminary settings)
 206  */
 207 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 208
 209 /*-----------------------------------------------------------------------
 210  * FLASH organization
 211  */
 212 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 213 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max num of sects on one chip */
 214
 215 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 216 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 217
 218 #if 0
 219 /* Start port with environment in flash; switch to EEPROM later */
 220 #define CONFIG_ENV_IS_IN_FLASH  1
 221 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE+0x40000)
 222 #define CONFIG_ENV_SIZE         0x40000
 223 #define CONFIG_ENV_SECT_SIZE    0x40000
 224 #else
 225 /* Final version: environment in EEPROM */
 226 #define CONFIG_ENV_IS_IN_EEPROM 1
 227 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58
 228 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 231 #define CONFIG_ENV_OFFSET               512
 232 #define CONFIG_ENV_SIZE         (2048 - 512)
 233 #endif
 234
 235 /*-----------------------------------------------------------------------
 236  * Hard Reset Configuration Words
 237  *
 238  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 239  * defines for the various registers affected by the HRCW e.g. changing
 240  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 241  */
 242 #if defined(CONFIG_BOOT_ROM)
 243 #define CONFIG_SYS_HRCW_MASTER          (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
 244 #else
 245 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
 246 #endif
 247
 248 /* no slaves so just fill with zeros */
 249 #define CONFIG_SYS_HRCW_SLAVE1          0
 250 #define CONFIG_SYS_HRCW_SLAVE2          0
 251 #define CONFIG_SYS_HRCW_SLAVE3          0
 252 #define CONFIG_SYS_HRCW_SLAVE4          0
 253 #define CONFIG_SYS_HRCW_SLAVE5          0
 254 #define CONFIG_SYS_HRCW_SLAVE6          0
 255 #define CONFIG_SYS_HRCW_SLAVE7          0
 256
 257 /*-----------------------------------------------------------------------
 258  * Internal Memory Mapped Register
 259  */
 260 #define CONFIG_SYS_IMMR         0xF0000000
 261
 262 /*-----------------------------------------------------------------------
 263  * Definitions for initial stack pointer and data area (in DPRAM)
 264  */
 265 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 266 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 267 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 268 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 269
 270 /*-----------------------------------------------------------------------
 271  * Start addresses for the final memory configuration
 272  * (Set up by the startup code)
 273  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 274  *
 275  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
 276  * is mapped at SDRAM_BASE2_PRELIM.
 277  */
 278 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 279 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
 280 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 281 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 282 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 283
 284 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 285 # define CONFIG_SYS_RAMBOOT
 286 #endif
 287
 288 #ifdef  CONFIG_PCI
 289 #define CONFIG_PCI_PNP
 290 #define CONFIG_EEPRO100
 291 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 292 #endif
 293
 294 /*-----------------------------------------------------------------------
 295  * Cache Configuration
 296  */
 297 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU              */
 298 #if defined(CONFIG_CMD_KGDB)
 299 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 300 #endif
 301
 302 /*-----------------------------------------------------------------------
 303  * HIDx - Hardware Implementation-dependent Registers                    2-11
 304  *-----------------------------------------------------------------------
 305  * HID0 also contains cache control - initially enable both caches and
 306  * invalidate contents, then the final state leaves only the instruction
 307  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 308  * but Soft reset does not.
 309  *
 310  * HID1 has only read-only information - nothing to set.
 311  */
 312 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 313                                 HID0_IFEM|HID0_ABE)
 314 #define CONFIG_SYS_HID0_FINAL   (HID0_ICE|HID0_IFEM|HID0_ABE)
 315 #define CONFIG_SYS_HID2 0
 316
 317 /*-----------------------------------------------------------------------
 318  * RMR - Reset Mode Register                                     5-5
 319  *-----------------------------------------------------------------------
 320  * turn on Checkstop Reset Enable
 321  */
 322 #define CONFIG_SYS_RMR          RMR_CSRE
 323
 324 /*-----------------------------------------------------------------------
 325  * BCR - Bus Configuration                                       4-25
 326  *-----------------------------------------------------------------------
 327  */
 328
 329 #define BCR_APD01       0x10000000
 330 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 331
 332 /*-----------------------------------------------------------------------
 333  * SIUMCR - SIU Module Configuration                             4-31
 334  *-----------------------------------------------------------------------
 335  */
 336 #if 0
 337 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
 338 #else
 339 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC10|SIUMCR_APPC10)
 340 #endif
 341
 342
 343 /*-----------------------------------------------------------------------
 344  * SYPCR - System Protection Control                             4-35
 345  * SYPCR can only be written once after reset!
 346  *-----------------------------------------------------------------------
 347  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 348  */
 349 #if defined(CONFIG_WATCHDOG)
 350 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 351                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 352 #else
 353 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 354                          SYPCR_SWRI|SYPCR_SWP)
 355 #endif /* CONFIG_WATCHDOG */
 356
 357 /*-----------------------------------------------------------------------
 358  * TMCNTSC - Time Counter Status and Control                     4-40
 359  *-----------------------------------------------------------------------
 360  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 361  * and enable Time Counter
 362  */
 363 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 364
 365 /*-----------------------------------------------------------------------
 366  * PISCR - Periodic Interrupt Status and Control                 4-42
 367  *-----------------------------------------------------------------------
 368  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 369  * Periodic timer
 370  */
 371 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
 372
 373 /*-----------------------------------------------------------------------
 374  * SCCR - System Clock Control                                   9-8
 375  *-----------------------------------------------------------------------
 376  */
 377 #define CONFIG_SYS_SCCR (SCCR_DFBRG00)
 378
 379 /*-----------------------------------------------------------------------
 380  * RCCR - RISC Controller Configuration                         13-7
 381  *-----------------------------------------------------------------------
 382  */
 383 #define CONFIG_SYS_RCCR 0
 384
 385 /*
 386  * Init Memory Controller:
 387  *
 388  * Bank Bus     Machine PortSz  Device
 389  * ---- ---     ------- ------  ------
 390  *  0   60x     GPCM    64 bit  FLASH
 391  *  1   60x     SDRAM   64 bit  SDRAM
 392  *
 393  */
 394
 395         /* Initialize SDRAM on local bus
 396          */
 397 #define CONFIG_SYS_INIT_LOCAL_SDRAM
 398
 399
 400 /* Minimum mask to separate preliminary
 401  * address ranges for CS[0:2]
 402  */
 403 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
 404
 405 /*
 406  * we use the same values for 32 MB and 128 MB SDRAM
 407  * refresh rate = 7.68 uS (100 MHz Bus Clock)
 408  */
 409 #define CONFIG_SYS_MPTPR        0x2000
 410 #define CONFIG_SYS_PSRT 0x16
 411
 412 #define CONFIG_SYS_MRS_OFFS     0x00000000
 413
 414
 415 #if defined(CONFIG_BOOT_ROM)
 416 /*
 417  * Bank 0 - Boot ROM (8 bit wide)
 418  */
 419 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 420                          BRx_PS_8                       |\
 421                          BRx_MS_GPCM_P                  |\
 422                          BRx_V)
 423
 424 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 425                          ORxG_CSNT                      |\
 426                          ORxG_ACS_DIV1                  |\
 427                          ORxG_SCY_5_CLK                 |\
 428                          ORxG_EHTR                      |\
 429                          ORxG_TRLX)
 430
 431 /*
 432  * Bank 1 - Flash (64 bit wide)
 433  */
 434 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 435                          BRx_PS_64                      |\
 436                          BRx_MS_GPCM_P                  |\
 437                          BRx_V)
 438
 439 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 440                          ORxG_CSNT                      |\
 441                          ORxG_ACS_DIV1                  |\
 442                          ORxG_SCY_5_CLK                 |\
 443                          ORxG_EHTR                      |\
 444                          ORxG_TRLX)
 445
 446 #else   /* ! CONFIG_BOOT_ROM */
 447
 448 /*
 449  * Bank 0 - Flash (64 bit wide)
 450  */
 451 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 452                          BRx_PS_64                      |\
 453                          BRx_MS_GPCM_P                  |\
 454                          BRx_V)
 455
 456 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 457                          ORxG_CSNT                      |\
 458                          ORxG_ACS_DIV1                  |\
 459                          ORxG_SCY_5_CLK                 |\
 460                          ORxG_EHTR                      |\
 461                          ORxG_TRLX)
 462
 463 /*
 464  * Bank 1 - Disk-On-Chip
 465  */
 466 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)     |\
 467                          BRx_PS_8                       |\
 468                          BRx_MS_GPCM_P                  |\
 469                          BRx_V)
 470
 471 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)        |\
 472                          ORxG_CSNT                      |\
 473                          ORxG_ACS_DIV1                  |\
 474                          ORxG_SCY_5_CLK                 |\
 475                          ORxG_EHTR                      |\
 476                          ORxG_TRLX)
 477
 478 #endif /* CONFIG_BOOT_ROM */
 479
 480 /* Bank 2 - SDRAM
 481  */
 482
 483 #ifndef CONFIG_SYS_RAMBOOT
 484 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)   |\
 485                          BRx_PS_64                      |\
 486                          BRx_MS_SDRAM_P                 |\
 487                          BRx_V)
 488
 489         /* SDRAM initialization values for 8-column chips
 490          */
 491 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 492                          ORxS_BPD_4                     |\
 493                          ORxS_ROWST_PBI0_A9             |\
 494                          ORxS_NUMR_12)
 495
 496 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 497                          PSDMR_BSMA_A14_A16             |\
 498                          PSDMR_SDA10_PBI0_A10           |\
 499                          PSDMR_RFRC_7_CLK               |\
 500                          PSDMR_PRETOACT_2W              |\
 501                          PSDMR_ACTTORW_2W               |\
 502                          PSDMR_LDOTOPRE_1C              |\
 503                          PSDMR_WRC_1C                   |\
 504                          PSDMR_CL_2)
 505
 506         /* SDRAM initialization values for 9-column chips
 507          */
 508 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 509                          ORxS_BPD_4                     |\
 510                          ORxS_ROWST_PBI0_A7             |\
 511                          ORxS_NUMR_13)
 512
 513 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 514                          PSDMR_BSMA_A13_A15             |\
 515                          PSDMR_SDA10_PBI0_A9            |\
 516                          PSDMR_RFRC_7_CLK               |\
 517                          PSDMR_PRETOACT_2W              |\
 518                          PSDMR_ACTTORW_2W               |\
 519                          PSDMR_LDOTOPRE_1C              |\
 520                          PSDMR_WRC_1C                   |\
 521                          PSDMR_CL_2)
 522
 523 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_9COL
 524 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_9COL
 525
 526 #endif /* CONFIG_SYS_RAMBOOT */
 527
 528 #endif  /* __CONFIG_H */