]> git.sur5r.net Git - u-boot/blob - include/configs/PM828.h
config: remove platform CONFIG_SYS_HZ definition part 1/2
[u-boot] / include / configs / PM828.h
1 /*
2  * (C) Copyright 2001-2005
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /*
9  * board/config.h - configuration options, board specific
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 #undef CONFIG_SYS_RAMBOOT
16
17 /*
18  * High Level Configuration Options
19  * (easy to change)
20  */
21
22 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU        */
23 #define CONFIG_PM828            1       /* ...on a PM828 module */
24 #define CONFIG_CPM2             1       /* Has a CPM2 */
25
26 #ifndef CONFIG_SYS_TEXT_BASE
27 #define CONFIG_SYS_TEXT_BASE    0x40000000      /* Standard: boot 64-bit flash */
28 #endif
29
30 #undef CONFIG_DB_CR826_J30x_ON          /* J30x jumpers on D.B. carrier */
31
32 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
33
34 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
35
36 #undef  CONFIG_BOOTARGS
37 #define CONFIG_BOOTCOMMAND                                                      \
38         "bootp;"                                                                \
39         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
40         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
41         "bootm"
42
43 /* enable I2C and select the hardware/software driver */
44 #define CONFIG_SYS_I2C
45 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
46 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
47 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
48 /*
49  * Software (bit-bang) I2C driver configuration
50  */
51 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
52 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
53 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
54 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
55 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
56                         else    iop->pdat &= ~0x00010000
57 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
58                         else    iop->pdat &= ~0x00020000
59 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
60
61
62 #define CONFIG_RTC_PCF8563
63 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
64
65 /*
66  * select serial console configuration
67  *
68  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
69  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
70  * for SCC).
71  *
72  * if CONFIG_CONS_NONE is defined, then the serial console routines must
73  * defined elsewhere (for example, on the cogent platform, there are serial
74  * ports on the motherboard which are used for the serial console - see
75  * cogent/cma101/serial.[ch]).
76  */
77 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
78 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
79 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
80 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
81
82 /*
83  * select ethernet configuration
84  *
85  * if CONFIG_ETHER_ON_SCC is selected, then
86  *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
87  *
88  * if CONFIG_ETHER_ON_FCC is selected, then
89  *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
90  *
91  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
92  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
93  */
94 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
95
96 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
97 #define CONFIG_ETHER_INDEX    1         /* which SCC channel for ethernet */
98
99 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
100 /*
101  * - Rx-CLK is CLK11
102  * - Tx-CLK is CLK10
103  */
104 #define CONFIG_ETHER_ON_FCC1
105 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
106 #ifndef CONFIG_DB_CR826_J30x_ON
107 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
108 #else
109 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
110 #endif
111 /*
112  * - Rx-CLK is CLK15
113  * - Tx-CLK is CLK14
114  */
115 #define CONFIG_ETHER_ON_FCC2
116 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
117 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
118 /*
119  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
120  * - Enable Full Duplex in FSMR
121  */
122 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
123 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
124
125 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
126 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
127
128 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
129 #define CONFIG_BAUDRATE         230400
130 #else
131 #define CONFIG_BAUDRATE         9600
132 #endif
133
134 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
135 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
136
137 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
138
139 /*
140  * BOOTP options
141  */
142 #define CONFIG_BOOTP_SUBNETMASK
143 #define CONFIG_BOOTP_GATEWAY
144 #define CONFIG_BOOTP_HOSTNAME
145 #define CONFIG_BOOTP_BOOTPATH
146 #define CONFIG_BOOTP_BOOTFILESIZE
147
148
149 /*
150  * Command line configuration.
151  */
152 #include <config_cmd_default.h>
153
154 #define CONFIG_CMD_BEDBUG
155 #define CONFIG_CMD_DATE
156 #define CONFIG_CMD_DHCP
157 #define CONFIG_CMD_EEPROM
158 #define CONFIG_CMD_I2C
159 #define CONFIG_CMD_NFS
160 #define CONFIG_CMD_SNTP
161
162 #ifdef CONFIG_PCI
163 #define CONFIG_PCI_INDIRECT_BRIDGE
164 #define CONFIG_CMD_PCI
165 #endif
166
167 /*
168  * Miscellaneous configurable options
169  */
170 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
171 #if defined(CONFIG_CMD_KGDB)
172 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
173 #else
174 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
175 #endif
176 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
177 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
178 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
179
180 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
181 #define CONFIG_SYS_MEMTEST_END 0x0C00000        /* 4 ... 12 MB in DRAM  */
182
183 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
184
185 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address                */
186
187 /*
188  * For booting Linux, the board info and command line data
189  * have to be in the first 8 MB of memory, since this is
190  * the maximum mapped by the Linux kernel during initialization.
191  */
192 #define CONFIG_SYS_BOOTMAPSZ         (8 << 20)       /* Initial Memory map for Linux */
193
194 /*-----------------------------------------------------------------------
195  * Flash and Boot ROM mapping
196  */
197
198 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
199 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
200 #define CONFIG_SYS_FLASH0_BASE          0x40000000
201 #define CONFIG_SYS_FLASH0_SIZE          0x02000000
202 #define CONFIG_SYS_DOC_BASE             0xFF800000
203 #define CONFIG_SYS_DOC_SIZE             0x00100000
204
205
206 /* Flash bank size (for preliminary settings)
207  */
208 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
209
210 /*-----------------------------------------------------------------------
211  * FLASH organization
212  */
213 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
214 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max num of sects on one chip */
215
216 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
217 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
218
219 #if 0
220 /* Start port with environment in flash; switch to EEPROM later */
221 #define CONFIG_ENV_IS_IN_FLASH  1
222 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE+0x40000)
223 #define CONFIG_ENV_SIZE         0x40000
224 #define CONFIG_ENV_SECT_SIZE    0x40000
225 #else
226 /* Final version: environment in EEPROM */
227 #define CONFIG_ENV_IS_IN_EEPROM 1
228 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58
229 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
232 #define CONFIG_ENV_OFFSET               512
233 #define CONFIG_ENV_SIZE         (2048 - 512)
234 #endif
235
236 /*-----------------------------------------------------------------------
237  * Hard Reset Configuration Words
238  *
239  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
240  * defines for the various registers affected by the HRCW e.g. changing
241  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
242  */
243 #if defined(CONFIG_BOOT_ROM)
244 #define CONFIG_SYS_HRCW_MASTER          (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
245 #else
246 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
247 #endif
248
249 /* no slaves so just fill with zeros */
250 #define CONFIG_SYS_HRCW_SLAVE1          0
251 #define CONFIG_SYS_HRCW_SLAVE2          0
252 #define CONFIG_SYS_HRCW_SLAVE3          0
253 #define CONFIG_SYS_HRCW_SLAVE4          0
254 #define CONFIG_SYS_HRCW_SLAVE5          0
255 #define CONFIG_SYS_HRCW_SLAVE6          0
256 #define CONFIG_SYS_HRCW_SLAVE7          0
257
258 /*-----------------------------------------------------------------------
259  * Internal Memory Mapped Register
260  */
261 #define CONFIG_SYS_IMMR         0xF0000000
262
263 /*-----------------------------------------------------------------------
264  * Definitions for initial stack pointer and data area (in DPRAM)
265  */
266 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
267 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
268 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
269 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
270
271 /*-----------------------------------------------------------------------
272  * Start addresses for the final memory configuration
273  * (Set up by the startup code)
274  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
275  *
276  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
277  * is mapped at SDRAM_BASE2_PRELIM.
278  */
279 #define CONFIG_SYS_SDRAM_BASE           0x00000000
280 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
281 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
282 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
283 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
284
285 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
286 # define CONFIG_SYS_RAMBOOT
287 #endif
288
289 #ifdef  CONFIG_PCI
290 #define CONFIG_PCI_PNP
291 #define CONFIG_EEPRO100
292 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
293 #endif
294
295 /*-----------------------------------------------------------------------
296  * Cache Configuration
297  */
298 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU              */
299 #if defined(CONFIG_CMD_KGDB)
300 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
301 #endif
302
303 /*-----------------------------------------------------------------------
304  * HIDx - Hardware Implementation-dependent Registers                    2-11
305  *-----------------------------------------------------------------------
306  * HID0 also contains cache control - initially enable both caches and
307  * invalidate contents, then the final state leaves only the instruction
308  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
309  * but Soft reset does not.
310  *
311  * HID1 has only read-only information - nothing to set.
312  */
313 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
314                                 HID0_IFEM|HID0_ABE)
315 #define CONFIG_SYS_HID0_FINAL   (HID0_ICE|HID0_IFEM|HID0_ABE)
316 #define CONFIG_SYS_HID2 0
317
318 /*-----------------------------------------------------------------------
319  * RMR - Reset Mode Register                                     5-5
320  *-----------------------------------------------------------------------
321  * turn on Checkstop Reset Enable
322  */
323 #define CONFIG_SYS_RMR          RMR_CSRE
324
325 /*-----------------------------------------------------------------------
326  * BCR - Bus Configuration                                       4-25
327  *-----------------------------------------------------------------------
328  */
329
330 #define BCR_APD01       0x10000000
331 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
332
333 /*-----------------------------------------------------------------------
334  * SIUMCR - SIU Module Configuration                             4-31
335  *-----------------------------------------------------------------------
336  */
337 #if 0
338 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
339 #else
340 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC10|SIUMCR_APPC10)
341 #endif
342
343
344 /*-----------------------------------------------------------------------
345  * SYPCR - System Protection Control                             4-35
346  * SYPCR can only be written once after reset!
347  *-----------------------------------------------------------------------
348  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
349  */
350 #if defined(CONFIG_WATCHDOG)
351 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
352                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
353 #else
354 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
355                          SYPCR_SWRI|SYPCR_SWP)
356 #endif /* CONFIG_WATCHDOG */
357
358 /*-----------------------------------------------------------------------
359  * TMCNTSC - Time Counter Status and Control                     4-40
360  *-----------------------------------------------------------------------
361  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
362  * and enable Time Counter
363  */
364 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
365
366 /*-----------------------------------------------------------------------
367  * PISCR - Periodic Interrupt Status and Control                 4-42
368  *-----------------------------------------------------------------------
369  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
370  * Periodic timer
371  */
372 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
373
374 /*-----------------------------------------------------------------------
375  * SCCR - System Clock Control                                   9-8
376  *-----------------------------------------------------------------------
377  */
378 #define CONFIG_SYS_SCCR (SCCR_DFBRG00)
379
380 /*-----------------------------------------------------------------------
381  * RCCR - RISC Controller Configuration                         13-7
382  *-----------------------------------------------------------------------
383  */
384 #define CONFIG_SYS_RCCR 0
385
386 /*
387  * Init Memory Controller:
388  *
389  * Bank Bus     Machine PortSz  Device
390  * ---- ---     ------- ------  ------
391  *  0   60x     GPCM    64 bit  FLASH
392  *  1   60x     SDRAM   64 bit  SDRAM
393  *
394  */
395
396         /* Initialize SDRAM on local bus
397          */
398 #define CONFIG_SYS_INIT_LOCAL_SDRAM
399
400
401 /* Minimum mask to separate preliminary
402  * address ranges for CS[0:2]
403  */
404 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
405
406 /*
407  * we use the same values for 32 MB and 128 MB SDRAM
408  * refresh rate = 7.68 uS (100 MHz Bus Clock)
409  */
410 #define CONFIG_SYS_MPTPR        0x2000
411 #define CONFIG_SYS_PSRT 0x16
412
413 #define CONFIG_SYS_MRS_OFFS     0x00000000
414
415
416 #if defined(CONFIG_BOOT_ROM)
417 /*
418  * Bank 0 - Boot ROM (8 bit wide)
419  */
420 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
421                          BRx_PS_8                       |\
422                          BRx_MS_GPCM_P                  |\
423                          BRx_V)
424
425 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
426                          ORxG_CSNT                      |\
427                          ORxG_ACS_DIV1                  |\
428                          ORxG_SCY_5_CLK                 |\
429                          ORxG_EHTR                      |\
430                          ORxG_TRLX)
431
432 /*
433  * Bank 1 - Flash (64 bit wide)
434  */
435 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
436                          BRx_PS_64                      |\
437                          BRx_MS_GPCM_P                  |\
438                          BRx_V)
439
440 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
441                          ORxG_CSNT                      |\
442                          ORxG_ACS_DIV1                  |\
443                          ORxG_SCY_5_CLK                 |\
444                          ORxG_EHTR                      |\
445                          ORxG_TRLX)
446
447 #else   /* ! CONFIG_BOOT_ROM */
448
449 /*
450  * Bank 0 - Flash (64 bit wide)
451  */
452 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
453                          BRx_PS_64                      |\
454                          BRx_MS_GPCM_P                  |\
455                          BRx_V)
456
457 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
458                          ORxG_CSNT                      |\
459                          ORxG_ACS_DIV1                  |\
460                          ORxG_SCY_5_CLK                 |\
461                          ORxG_EHTR                      |\
462                          ORxG_TRLX)
463
464 /*
465  * Bank 1 - Disk-On-Chip
466  */
467 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)     |\
468                          BRx_PS_8                       |\
469                          BRx_MS_GPCM_P                  |\
470                          BRx_V)
471
472 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)        |\
473                          ORxG_CSNT                      |\
474                          ORxG_ACS_DIV1                  |\
475                          ORxG_SCY_5_CLK                 |\
476                          ORxG_EHTR                      |\
477                          ORxG_TRLX)
478
479 #endif /* CONFIG_BOOT_ROM */
480
481 /* Bank 2 - SDRAM
482  */
483
484 #ifndef CONFIG_SYS_RAMBOOT
485 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)   |\
486                          BRx_PS_64                      |\
487                          BRx_MS_SDRAM_P                 |\
488                          BRx_V)
489
490         /* SDRAM initialization values for 8-column chips
491          */
492 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
493                          ORxS_BPD_4                     |\
494                          ORxS_ROWST_PBI0_A9             |\
495                          ORxS_NUMR_12)
496
497 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
498                          PSDMR_BSMA_A14_A16             |\
499                          PSDMR_SDA10_PBI0_A10           |\
500                          PSDMR_RFRC_7_CLK               |\
501                          PSDMR_PRETOACT_2W              |\
502                          PSDMR_ACTTORW_2W               |\
503                          PSDMR_LDOTOPRE_1C              |\
504                          PSDMR_WRC_1C                   |\
505                          PSDMR_CL_2)
506
507         /* SDRAM initialization values for 9-column chips
508          */
509 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
510                          ORxS_BPD_4                     |\
511                          ORxS_ROWST_PBI0_A7             |\
512                          ORxS_NUMR_13)
513
514 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
515                          PSDMR_BSMA_A13_A15             |\
516                          PSDMR_SDA10_PBI0_A9            |\
517                          PSDMR_RFRC_7_CLK               |\
518                          PSDMR_PRETOACT_2W              |\
519                          PSDMR_ACTTORW_2W               |\
520                          PSDMR_LDOTOPRE_1C              |\
521                          PSDMR_WRC_1C                   |\
522                          PSDMR_CL_2)
523
524 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_9COL
525 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_9COL
526
527 #endif /* CONFIG_SYS_RAMBOOT */
528
529 #endif  /* __CONFIG_H */