2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * pm854 board configuration file
28 * Please refer to doc/README.mpc85xx for more info.
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
37 /* High Level Configuration Options */
38 #define CONFIG_BOOKE 1 /* BOOKE */
39 #define CONFIG_E500 1 /* BOOKE e500 family */
40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41 #define CONFIG_MPC8540 1 /* MPC8540 specific */
42 #define CONFIG_PM854 1 /* PM854 board specific */
45 #define CONFIG_TSEC_ENET /* tsec ethernet support */
46 #define CONFIG_ENV_OVERWRITE
47 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/
48 #define CONFIG_DDR_ECC /* only for ECC DDR module */
49 #define CONFIG_DDR_DLL /* possible DLL fix needed */
50 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
56 * Two valid values are:
60 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
61 * is likely the desired value here, so that is now the default.
62 * The board, however, can run at 66MHz. In any event, this value
63 * must match the settings of some switches. Details can be found
64 * in the README.mpc85xxads.
67 #ifndef CONFIG_SYS_CLK_FREQ
68 #define CONFIG_SYS_CLK_FREQ 66000000
73 * These can be toggled for performance analysis, otherwise use default.
75 #define CONFIG_L2_CACHE /* toggle L2 cache */
76 #define CONFIG_BTB /* toggle branch predition */
77 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
79 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
81 #undef CFG_DRAM_TEST /* memory test, takes time */
82 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
83 #define CFG_MEMTEST_END 0x00400000
87 * Base addresses -- Note these are effective addresses where the
88 * actual resources get mapped (not physical addresses)
90 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
91 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
92 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
98 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
99 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
101 #if defined(CONFIG_SPD_EEPROM)
103 * Determine DDR configuration from I2C interface.
105 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
109 * Manually set up DDR parameters
111 #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
112 #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
113 #define CFG_DDR_CS0_CONFIG 0x80000102
114 #define CFG_DDR_TIMING_1 0x47444321
115 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
116 #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
117 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
118 #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
123 * SDRAM on the Local Bus
125 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
126 #define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */
128 #define CFG_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */
129 #define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
131 #define CFG_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */
132 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
133 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */
134 #undef CFG_FLASH_CHECKSUM
135 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
136 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
138 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
141 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
148 #undef CONFIG_CLOCKS_IN_MHZ
152 * Local Bus Definitions
155 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
156 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
157 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
158 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
161 #define CONFIG_L1_INIT_RAM
162 #define CFG_INIT_RAM_LOCK 1
163 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
164 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
166 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
167 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
168 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
170 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
171 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
174 #define CONFIG_CONS_INDEX 1
175 #undef CONFIG_SERIAL_SOFTWARE_FIFO
177 #define CFG_NS16550_SERIAL
178 #define CFG_NS16550_REG_SIZE 1
179 #define CFG_NS16550_CLK get_bus_freq(0)
181 #define CFG_BAUDRATE_TABLE \
182 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
184 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
185 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
187 /* Use the HUSH parser */
188 #define CFG_HUSH_PARSER
189 #ifdef CFG_HUSH_PARSER
190 #define CFG_PROMPT_HUSH_PS2 "> "
194 #define CONFIG_HARD_I2C /* I2C with hardware support*/
195 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
196 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
197 #define CFG_I2C_SLAVE 0x7F
198 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
201 * EEPROM configuration
203 #define CFG_I2C_EEPROM_ADDR 0x58
204 #define CFG_I2C_EEPROM_ADDR_LEN 1
205 #define CFG_EEPROM_PAGE_WRITE_BITS 4
206 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
211 #define CONFIG_RTC_PCF8563
212 #define CFG_I2C_RTC_ADDR 0x51
215 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
216 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
217 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
221 * Addresses are mapped 1-1.
223 #define CFG_PCI1_MEM_BASE 0x80000000
224 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
225 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
226 #define CFG_PCI1_IO_BASE 0xe2000000
227 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
228 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
230 #if defined(CONFIG_PCI)
232 #define CONFIG_NET_MULTI
233 #define CONFIG_PCI_PNP /* do pci plug-and-play */
235 #undef CONFIG_EEPRO100
238 #if !defined(CONFIG_PCI_PNP)
239 #define PCI_ENET0_IOADDR 0xe0000000
240 #define PCI_ENET0_MEMADDR 0xe0000000
241 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
244 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
245 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
247 #endif /* CONFIG_PCI */
250 #if defined(CONFIG_TSEC_ENET)
252 #ifndef CONFIG_NET_MULTI
253 #define CONFIG_NET_MULTI 1
256 #define CONFIG_MII 1 /* MII PHY management */
257 #define CONFIG_MPC85XX_TSEC1 1
258 #define CONFIG_MPC85XX_TSEC2 1
259 #define TSEC1_PHY_ADDR 2
260 #define TSEC2_PHY_ADDR 3
261 #define TSEC1_PHYIDX 0
262 #define TSEC2_PHYIDX 0
264 #define CONFIG_MPC85XX_FEC 1
265 #define FEC_PHY_ADDR 1
268 #define CONFIG_ETHPRIME "MOTO ENET0"
270 #define CONFIG_HAS_ETH1 1
271 #define CONFIG_HAS_ETH2 1
273 #endif /* CONFIG_TSEC_ENET */
280 #define CFG_ENV_IS_IN_FLASH 1
281 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000)
282 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
283 #define CFG_ENV_SIZE 0x2000
285 #define CFG_NO_FLASH 1 /* Flash is not usable now */
286 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
287 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
288 #define CFG_ENV_SIZE 0x2000
291 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
292 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
294 #if defined(CFG_RAMBOOT)
295 #if defined(CONFIG_PCI)
296 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
304 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
312 #if defined(CONFIG_PCI)
313 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
320 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
328 #include <cmd_confdefs.h>
330 #undef CONFIG_WATCHDOG /* watchdog disabled */
333 * Miscellaneous configurable options
335 #define CFG_LONGHELP /* undef to save memory */
336 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
337 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
339 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
340 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
342 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
345 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
346 #define CFG_MAXARGS 16 /* max number of command args */
347 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
348 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
352 * For booting Linux, the board info and command line data
353 * have to be in the first 8 MB of memory, since this is
354 * the maximum mapped by the Linux kernel during initialization.
356 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
358 /* Cache Configuration */
359 #define CFG_DCACHE_SIZE 32768
360 #define CFG_CACHELINE_SIZE 32
361 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
362 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
366 * Internal Definitions
370 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
371 #define BOOTFLAG_WARM 0x02 /* Software reboot */
373 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
374 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
375 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
380 * Environment Configuration
383 /* The mac addresses for all ethernet interface */
384 #if defined(CONFIG_TSEC_ENET)
385 #define CONFIG_ETHADDR 00:40:42:01:00:00
386 #define CONFIG_ETH1ADDR 00:40:42:01:00:01
387 #define CONFIG_ETH2ADDR 00:40:42:01:00:02
390 #define CONFIG_IPADDR 192.168.0.103
392 #define CONFIG_HOSTNAME PM854
393 #define CONFIG_ROOTPATH /opt/eldk30/ppc_82xx
394 #define CONFIG_BOOTFILE uImage
396 #define CONFIG_SERVERIP 192.168.0.54
397 #define CONFIG_GATEWAYIP 192.168.0.1
398 #define CONFIG_NETMASK 255.255.255.0
400 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
402 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
403 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
405 #define CONFIG_BAUDRATE 9600
407 #define CONFIG_EXTRA_ENV_SETTINGS \
409 "consoledev=ttyS0\0" \
410 "ramdiskaddr=400000\0" \
411 "ramdiskfile=uRamdisk\0"
413 #define CONFIG_NFSBOOTCOMMAND \
414 "setenv bootargs root=/dev/nfs rw " \
415 "nfsroot=$serverip:$rootpath " \
416 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
417 "console=$consoledev,$baudrate $othbootargs;" \
418 "tftp $loadaddr $bootfile;" \
421 #define CONFIG_RAMBOOTCOMMAND \
422 "setenv bootargs root=/dev/ram rw " \
423 "console=$consoledev,$baudrate $othbootargs;" \
424 "tftp $ramdiskaddr $ramdiskfile;" \
425 "tftp $loadaddr $bootfile;" \
426 "bootm $loadaddr $ramdiskaddr"
428 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
430 #endif /* __CONFIG_H */