6 * Simple Network Magic Corporation
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * board/config.h - configuration options, board specific
37 /* various debug settings */
38 #undef CFG_DEVICE_NULLDEV /* null device */
39 #undef CONFIG_SILENT_CONSOLE /* silent console */
40 #undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
41 #undef DEBUG /* debug output code */
42 #undef DEBUG_FLASH /* debug flash code */
43 #undef FLASH_DEBUG /* debug fash code */
44 #undef DEBUG_ENV /* debug environment code */
46 #define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
47 #define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
50 * High Level Configuration Options
53 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
54 #define CONFIG_QS850 1 /* ...on a QS850 module */
55 #define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */
57 /* Select the target clock speed */
58 #undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */
59 #undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */
60 #undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */
61 #define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */
62 #undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */
64 #ifdef CONFIG_CLOCK_16MHZ
65 #define CONFIG_CLOCK_MULT 512
68 #ifdef CONFIG_CLOCK_33MHZ
69 #define CONFIG_CLOCK_MULT 1024
72 #ifdef CONFIG_CLOCK_50MHZ
73 #define CONFIG_CLOCK_MULT 1525
76 #ifdef CONFIG_CLOCK_66MHZ
77 #define CONFIG_CLOCK_MULT 2048
80 #ifdef CONFIG_CLOCK_80MHZ
81 #define CONFIG_CLOCK_MULT 2441
84 /* choose flash size, 4Mb or 8Mb */
85 #define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */
86 #undef CONFIG_FLASH_8MB /* board has 8Mb flash */
88 #define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */
90 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
91 #undef CONFIG_8xx_CONS_SMC2
92 #undef CONFIG_8xx_CONS_NONE
94 #define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
96 #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
98 /* Define default IP addresses */
99 #define CONFIG_IPADDR 192.168.1.99 /* own ip address */
100 #define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */
102 /* message to say directly after booting */
103 #define CONFIG_PREBOOT "echo '';" \
105 "echo 'run boot_nfs to boot to NFS';" \
106 "echo 'run boot_flash to boot to flash';" \
108 "echo 'run flash_rootfs to install a new rootfs';" \
109 "echo 'run flash_env to clear the env sector';" \
110 "echo 'run flash_rw to clear the rw fs';" \
111 "echo 'run flash_uboot to install a new u-boot';" \
112 "echo 'run flash_kernel to install a new kernel';"
114 /* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
115 #define CONFIG_BOOTDELAY 5
116 #define CONFIG_BOOTCOMMAND "run boot_nfs"
118 #undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */
120 /* Our flash filesystem looks like this
123 * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb)
124 * ffec 0000 - ffed ffff read-write filesystem (ext2)
125 * ffee 0000 - ffef ffff environment
126 * fff0 0000 - fff1 ffff u-boot
127 * fff2 0000 - ffff ffff linux kernel
130 * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb)
131 * ffec 0000 - ffed ffff read-write filesystem (ext2)
132 * ffee 0000 - ffef ffff environment
133 * fff0 0000 - fff1 ffff u-boot
134 * fff2 0000 - ffff ffff linux kernel
138 /* environment for 4Mb board */
139 #ifdef CONFIG_FLASH_4MB
140 #define CONFIG_EXTRA_ENV_SETTINGS \
144 "ethaddr=00:01:02:B4:36:56\0" \
145 "rootpath=/exports/rootfs\0" \
146 "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
147 /* fill in variables */ \
148 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
149 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
150 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
152 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
153 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
154 /* reinstall flash parts */ \
155 "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
156 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
157 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
158 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
159 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
160 #endif /* CONFIG_FLASH_4MB */
162 /* environment for 8Mb board */
163 #ifdef CONFIG_FLASH_8MB
164 #define CONFIG_EXTRA_ENV_SETTINGS \
168 "ethaddr=00:01:02:B4:36:56\0" \
169 "rootpath=/exports/rootfs\0" \
170 "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
171 /* fill in variables */ \
172 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
173 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
174 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
176 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
177 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
178 /* reinstall flash parts */ \
179 "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
180 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
181 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
182 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
183 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
184 #endif /* CONFIG_FLASH_8MB */
186 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
187 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
188 #undef CONFIG_WATCHDOG /* watchdog disabled */
189 #undef CONFIG_STATUS_LED /* Status LED disabled */
190 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
192 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
194 #undef CONFIG_MAC_PARTITION
195 #undef CONFIG_DOS_PARTITION
197 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
201 * Command line configuration.
204 #define CONFIG_CMD_BDI
205 #define CONFIG_CMD_BOOTD
206 #define CONFIG_CMD_CONSOLE
207 #define CONFIG_CMD_DATE
208 #define CONFIG_CMD_ENV
209 #define CONFIG_CMD_FLASH
210 #define CONFIG_CMD_IMI
211 #define CONFIG_CMD_IMMAP
212 #define CONFIG_CMD_MEMORY
213 #define CONFIG_CMD_NET
214 #define CONFIG_CMD_RUN
217 /*-----------------------------------------------------------------------
218 * Environment variable storage is in FLASH, one sector before U-boot
220 #define CFG_ENV_IS_IN_FLASH 1
221 #define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */
222 #define CFG_ENV_SIZE 0x2000 /* 8kb */
223 #define CFG_ENV_ADDR 0xffee0000 /* address of env sector */
225 /*-----------------------------------------------------------------------
226 * Miscellaneous configurable options
228 #define CFG_LONGHELP /* undef to save memory */
229 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
231 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
232 #define CFG_PROMPT_HUSH_PS2 "> "
234 #if defined(CONFIG_CMD_KGDB)
235 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
237 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
239 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
240 #define CFG_MAXARGS 16 /* max number of command args */
241 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
243 #define CFG_MEMTEST_START 0x0400000 /* memtest works */
244 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
246 #define CFG_LOAD_ADDR 0x400000 /* default load address */
248 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
250 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
252 /*-----------------------------------------------------------------------
253 * Low Level Configuration Settings
254 * (address mappings, register initial values, etc.)
255 * You should know what you are doing if you make changes here.
258 /*-----------------------------------------------------------------------
259 * Internal Memory Mapped Register
261 #define CFG_IMMR 0xFF000000
263 /*-----------------------------------------------------------------------
264 * Definitions for initial stack pointer and data area (in DPRAM)
266 #define CFG_INIT_RAM_ADDR CFG_IMMR
267 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
268 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
269 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
270 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
272 /*-----------------------------------------------------------------------
273 * Start addresses for the final memory configuration
274 * (Set up by the startup code)
275 * Please note that CFG_SDRAM_BASE _must_ start at 0
277 #define CFG_SDRAM_BASE 0x00000000
278 #define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */
280 #define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */
281 #define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */
283 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
284 #define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */
285 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
288 * For booting Linux, the board info and command line data
289 * have to be in the first 8 MB of memory, since this is
290 * the maximum mapped by the Linux kernel during initialization.
292 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
294 /*-----------------------------------------------------------------------
295 * TODO flash parameters
296 * FLASH organization for Intel Strataflash
298 #undef CFG_FLASH_16BIT /* 32-bit wide flash memory */
299 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
300 #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
302 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
303 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
305 /*-----------------------------------------------------------------------
306 * Cache Configuration
308 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
309 #if defined(CONFIG_CMD_KGDB)
310 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
313 /*-----------------------------------------------------------------------
314 * SYPCR - System Protection Control 11-9
315 * SYPCR can only be written once after reset!
316 *-----------------------------------------------------------------------
317 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
320 #ifdef CONFIG_WATCHDOG
321 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
323 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
326 /*-----------------------------------------------------------------------
327 * SIUMCR - SIU Module Configuration 11-6
328 *-----------------------------------------------------------------------
330 #define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
332 /*-----------------------------------------------------------------------
333 * TBSCR - Time Base Status and Control 11-26
334 *-----------------------------------------------------------------------
336 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
338 /*-----------------------------------------------------------------------
339 * RTCSC - Real-Time Clock Status and Control Register 11-27
340 *-----------------------------------------------------------------------
342 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
344 /*-----------------------------------------------------------------------
345 * PISCR - Periodic Interrupt Status and Control 11-31
346 *-----------------------------------------------------------------------
348 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
350 /*-----------------------------------------------------------------------
351 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
352 *-----------------------------------------------------------------------
355 /* MF (Multiplication Factor of SPLL) */
356 /* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */
357 #define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20)
358 #define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
360 /*-----------------------------------------------------------------------
361 * SCCR - System Clock and reset Control Register 15-27
362 *-----------------------------------------------------------------------
364 #if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
365 #define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
366 #define CFG_BRGCLK_PRESCALE 1
369 #if defined(CONFIG_CLOCK_66MHZ)
370 #define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
371 #define CFG_BRGCLK_PRESCALE 4
374 #if defined(CONFIG_CLOCK_80MHZ)
375 #define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
376 #define CFG_BRGCLK_PRESCALE 4
379 #define SCCR_MASK CFG_SCCR
381 /*-----------------------------------------------------------------------
382 * Debug Enable Register
383 * 0x73E67C0F - All interrupts handled by BDM
384 * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
385 *-----------------------------------------------------------------------
386 #define CFG_DER 0x73E67C0F
387 #define CFG_DER 0x0082400F
389 #-------------------------------------------------------------------------
390 # Program the Debug Enable Register (DER). This register provides the user
391 # with the reason for entering into the debug mode. We want all conditions
392 # to end up as an exception. We don't want to enter into debug mode for
393 # any condition. See the back of of the Development Support section of the
394 # MPC860 User Manual for a description of this register.
395 #-------------------------------------------------------------------------
399 /*-----------------------------------------------------------------------
400 * Memory Controller Initialization Constants
401 *-----------------------------------------------------------------------
405 * BR0 and OR0 (AMD dual FLASH devices)
406 * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
408 #define CFG_PRELIM_OR_AM
409 #define CFG_OR_TIMING_FLASH
412 *-----------------------------------------------------------------------
413 * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
414 * flash that resides on the QS850.
415 *-----------------------------------------------------------------------
418 /* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
419 /* represents a minumum 32K block size. */
420 #define vBR0_BA ((0xFF80 << 16) + (0 << 15))
421 #define CFG_BR0_PRELIM (vBR0_BA | BR_V)
423 /* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */
424 /* which defines a 8 Mbyte memory block. */
425 #define vOR0_AM ((0xFF80 << 16) + (0 << 15))
427 #if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
428 /* 0101 = Add a 5 clock cycle wait state */
429 #define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
432 #if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
433 /* 0011 = Add a 3 clock cycle wait state */
434 /* 29.8ns clock * (3 + 2) = 149ns cycle time */
435 #define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
438 #if defined(CONFIG_CLOCK_16MHZ)
439 /* 0010 = Add a 2 clock cycle wait state */
440 #define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
444 * BR1 and OR1 (SDRAM)
445 * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
446 * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
447 * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
448 * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
451 #define SDRAM_BASE 0x00000000 /* SDRAM bank */
452 #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
454 /* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
455 * represents a 128 Mbyte block the DRAM in
458 #define vOR1_AM ((0xF800 << 16) + (0 << 15))
459 #define vBR1_BA ((0x0000 << 16) + (0 << 15))
460 #define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI)
461 #define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V)
463 /* Machine A Mode Register */
465 /* PTA Periodic Timer A */
467 #if defined(CONFIG_CLOCK_80MHZ)
468 #define vMAMR_PTA (19 << 24)
471 #if defined(CONFIG_CLOCK_66MHZ)
472 #define vMAMR_PTA (16 << 24)
475 #if defined(CONFIG_CLOCK_50MHZ)
476 #define vMAMR_PTA (195 << 24)
479 #if defined(CONFIG_CLOCK_33MHZ)
480 #define vMAMR_PTA (131 << 24)
483 #if defined(CONFIG_CLOCK_16MHZ)
484 #define vMAMR_PTA (65 << 24)
487 /* For boards with 16M of SDRAM */
488 #define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
489 #define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
490 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
492 /* For boards with 32M of SDRAM */
493 #define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */
494 #define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
495 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
498 /* Memory Periodic Timer Prescaler Register */
500 #if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
502 #define CFG_MPTPR 0x02
505 #if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
507 #define CFG_MPTPR 0x04
511 * BR2 and OR2 (Unused)
512 * Base address = 0xF020_0000 - 0xF020_0FFF
515 #define CFG_OR2_PRELIM 0xFFF00000
516 #define CFG_BR2_PRELIM 0xF0200000
519 * BR3 and OR3 (External Bus CS3)
520 * Base address = 0xF030_0000 - 0xF030_0FFF
523 #define CFG_OR3_PRELIM 0xFFF00000
524 #define CFG_BR3_PRELIM 0xF0300000
527 * BR4 and OR4 (External Bus CS3)
528 * Base address = 0xF040_0000 - 0xF040_0FFF
531 #define CFG_OR4_PRELIM 0xFFF00000
532 #define CFG_BR4_PRELIM 0xF0400000
536 * BR4 and OR4 (External Bus CS3)
537 * Base address = 0xF050_0000 - 0xF050_0FFF
540 #define CFG_OR5_PRELIM 0xFFF00000
541 #define CFG_BR5_PRELIM 0xF0500000
544 * BR6 and OR6 (Unused)
545 * Base address = 0xF060_0000 - 0xF060_0FFF
548 #define CFG_OR6_PRELIM 0xFFF00000
549 #define CFG_BR6_PRELIM 0xF0600000
552 * BR7 and OR7 (Unused)
553 * Base address = 0xF070_0000 - 0xF070_0FFF
556 #define CFG_OR7_PRELIM 0xFFF00000
557 #define CFG_BR7_PRELIM 0xF0700000
560 * Internal Definitions
564 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
565 #define BOOTFLAG_WARM 0x02 /* Software reboot */
570 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
571 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
574 #endif /* __CONFIG_H */