2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
21 #define CONFIG_R360MPI 1
23 #define CONFIG_SYS_TEXT_BASE 0x40000000
26 #define CONFIG_MPC8XX_LCD
27 #undef CONFIG_EDT32F10
28 #define CONFIG_SHARP_LQ057Q3DC02
30 #define CONFIG_SPLASH_SCREEN
32 #define MPC8XX_FACT 1 /* Multiply by 1 */
33 #define MPC8XX_XIN 50000000 /* 50 MHz in */
34 #define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */
36 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
37 #undef CONFIG_8xx_CONS_SMC2
38 #undef CONFIG_8xx_CONS_NONE
39 #define CONFIG_BAUDRATE 115200 /* console baudrate in bps */
41 #define CONFIG_BOOTDELAY 0 /* immediate boot */
43 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
46 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
48 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
50 #undef CONFIG_BOOTARGS
51 #define CONFIG_BOOTCOMMAND \
53 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
54 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
57 #undef CONFIG_SCC1_ENET
58 #define CONFIG_SCC2_ENET
60 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
61 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
63 #define CONFIG_MISC_INIT_R /* have misc_init_r() function */
65 #undef CONFIG_WATCHDOG /* watchdog disabled */
67 #define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
72 #define CONFIG_BOOTP_SUBNETMASK
73 #define CONFIG_BOOTP_GATEWAY
74 #define CONFIG_BOOTP_HOSTNAME
75 #define CONFIG_BOOTP_BOOTPATH
76 #define CONFIG_BOOTP_BOOTFILESIZE
78 #define CONFIG_MAC_PARTITION
79 #define CONFIG_DOS_PARTITION
81 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
83 #define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
84 #undef CONFIG_SORT_I2C /* To I2C with software support */
85 #define CONFIG_SYS_I2C_SPEED 4700 /* I2C speed and slave address */
86 #define CONFIG_SYS_I2C_SLAVE 0x7F
89 * Software (bit-bang) I2C driver configuration
91 #define PB_SCL 0x00000020 /* PB 26 */
92 #define PB_SDA 0x00000010 /* PB 27 */
94 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
95 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
96 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
97 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
98 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
99 else immr->im_cpm.cp_pbdat &= ~PB_SDA
100 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
101 else immr->im_cpm.cp_pbdat &= ~PB_SCL
102 #define I2C_DELAY udelay(50)
104 #define CONFIG_SYS_I2C_LCD_ADDR 0x8 /* LCD Control */
105 #define CONFIG_SYS_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
106 #define CONFIG_SYS_I2C_TEM_ADDR 0x49 /* Temperature Sensors */
110 * Command line configuration.
112 #include <config_cmd_default.h>
114 #define CONFIG_CMD_BMP
115 #define CONFIG_CMD_BSP
116 #define CONFIG_CMD_DATE
117 #define CONFIG_CMD_DHCP
118 #define CONFIG_CMD_I2C
119 #define CONFIG_CMD_IDE
120 #define CONFIG_CMD_JFFS2
121 #define CONFIG_CMD_NFS
122 #define CONFIG_CMD_PCMCIA
123 #define CONFIG_CMD_SNTP
127 * Miscellaneous configurable options
129 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* we need the null device */
130 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* must set console from env */
132 #define CONFIG_SYS_LONGHELP /* undef to save memory */
133 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
134 #if defined(CONFIG_CMD_KGDB)
135 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
137 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
139 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
140 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
141 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
143 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
144 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
146 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
148 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
153 /* No command line, one static partition
154 * use all the space starting at offset 3MB*/
155 #undef CONFIG_CMD_MTDPARTS
156 #define CONFIG_JFFS2_DEV "nor0"
157 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
158 #define CONFIG_JFFS2_PART_OFFSET 0x00300000
160 /* mtdparts command line support */
162 #define CONFIG_CMD_MTDPARTS
163 #define MTDIDS_DEFAULT "nor0=r360-0"
164 #define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)"
168 * Low Level Configuration Settings
169 * (address mappings, register initial values, etc.)
170 * You should know what you are doing if you make changes here.
172 /*-----------------------------------------------------------------------
173 * Internal Memory Mapped Register
175 #define CONFIG_SYS_IMMR 0xFF000000
177 /*-----------------------------------------------------------------------
178 * Definitions for initial stack pointer and data area (in DPRAM)
180 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
181 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
182 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
183 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
185 /*-----------------------------------------------------------------------
186 * Start addresses for the final memory configuration
187 * (Set up by the startup code)
188 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
190 #define CONFIG_SYS_SDRAM_BASE 0x00000000
191 #define CONFIG_SYS_FLASH_BASE 0x40000000
193 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
195 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
197 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
198 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
201 * For booting Linux, the board info and command line data
202 * have to be in the first 8 MB of memory, since this is
203 * the maximum mapped by the Linux kernel during initialization.
205 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
207 /*-----------------------------------------------------------------------
210 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
211 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
213 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
214 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
216 #define CONFIG_ENV_IS_IN_FLASH 1
217 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment */
218 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
219 #define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
220 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
222 /*-----------------------------------------------------------------------
223 * Cache Configuration
225 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
226 #if defined(CONFIG_CMD_KGDB)
227 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
230 /*-----------------------------------------------------------------------
231 * SYPCR - System Protection Control 11-9
232 * SYPCR can only be written once after reset!
233 *-----------------------------------------------------------------------
234 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
236 #if defined(CONFIG_WATCHDOG)
237 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
238 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
240 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
243 /*-----------------------------------------------------------------------
244 * SIUMCR - SIU Module Configuration 11-6
245 *-----------------------------------------------------------------------
246 * PCMCIA config., multi-function pin tri-state
248 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
250 /*-----------------------------------------------------------------------
251 * TBSCR - Time Base Status and Control 11-26
252 *-----------------------------------------------------------------------
253 * Clear Reference Interrupt Status, Timebase freezing enabled
255 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
257 /*-----------------------------------------------------------------------
258 * RTCSC - Real-Time Clock Status and Control Register 11-27
259 *-----------------------------------------------------------------------
261 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
263 /*-----------------------------------------------------------------------
264 * PISCR - Periodic Interrupt Status and Control 11-31
265 *-----------------------------------------------------------------------
266 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
268 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
270 /*-----------------------------------------------------------------------
271 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
272 *-----------------------------------------------------------------------
273 * Reset PLL lock status sticky bit, timer expired status bit and timer
274 * interrupt status bit
276 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
278 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
279 #define CONFIG_SYS_PLPRCR \
280 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
281 #else /* up to 50 MHz we use a 1:1 clock */
282 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
283 #endif /* CONFIG_80MHz */
285 /*-----------------------------------------------------------------------
286 * SCCR - System Clock and reset Control Register 15-27
287 *-----------------------------------------------------------------------
288 * Set clock output, timebase and RTC source and divider,
289 * power management and some other internal clocks
291 #define SCCR_MASK SCCR_EBDF11
292 #define CONFIG_SYS_SCCR (SCCR_TBS | \
293 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
294 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
297 /*-----------------------------------------------------------------------
299 *-----------------------------------------------------------------------
302 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
303 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
304 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
305 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
306 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
307 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
308 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
309 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
311 /*-----------------------------------------------------------------------
312 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
313 *-----------------------------------------------------------------------
317 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
318 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
320 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
321 #undef CONFIG_IDE_LED /* LED for ide not supported */
322 #undef CONFIG_IDE_RESET /* reset for ide not supported */
324 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
325 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
327 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
329 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
331 /* Offset for data I/O */
332 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
334 /* Offset for normal register accesses */
335 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
337 /* Offset for alternate registers */
338 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
341 /*-----------------------------------------------------------------------
343 *-----------------------------------------------------------------------
346 #define CONFIG_SYS_DER 0
349 * Init Memory Controller:
351 * BR0/1 and OR0/1 (FLASH)
354 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
356 /* used to re-map FLASH both when starting from SRAM or FLASH:
357 * restrict access enough to keep SRAM working (if any)
358 * but not too much to meddle with FLASH accesses
360 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
361 #define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
366 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
368 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
369 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
370 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
374 * BR2 and OR2 (SDRAM)
377 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
378 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
380 #define CONFIG_SYS_PRELIM_OR2_AM 0xF8000000 /* OR addr mask */
382 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
383 #define CONFIG_SYS_OR_TIMING_SDRAM (OR_ACS_DIV1 | OR_CSNT_SAM | \
384 OR_SCY_0_CLK | OR_G5LS)
386 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR2_AM | CONFIG_SYS_OR_TIMING_SDRAM )
387 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
390 * BR3 and OR3 (CAN Controller)
392 #ifdef CONFIG_CAN_DRIVER
393 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN base address */
394 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
395 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA |OR_BI)
396 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
397 BR_PS_8 | BR_MS_UPMB | BR_V)
398 #endif /* CONFIG_CAN_DRIVER */
402 * Memory Periodic Timer Prescaler
404 * The Divider for PTA (refresh timer) configuration is based on an
405 * example SDRAM configuration (64 MBit, one bank). The adjustment to
406 * the number of chip selects (NCS) and the actually needed refresh
407 * rate is done by setting MPTPR.
409 * PTA is calculated from
410 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
412 * gclk CPU clock (not bus clock!)
413 * Trefresh Refresh cycle * 4 (four word bursts used)
415 * 4096 Rows from SDRAM example configuration
416 * 1000 factor s -> ms
417 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
418 * 4 Number of refresh cycles per period
419 * 64 Refresh cycle in ms per number of rows
420 * --------------------------------------------
421 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
423 * 50 MHz => 50.000.000 / Divider = 98
424 * 66 Mhz => 66.000.000 / Divider = 129
425 * 80 Mhz => 80.000.000 / Divider = 156
427 #if defined(CONFIG_80MHz)
428 #define CONFIG_SYS_MAMR_PTA 156
429 #elif defined(CONFIG_66MHz)
430 #define CONFIG_SYS_MAMR_PTA 129
432 #define CONFIG_SYS_MAMR_PTA 98
433 #endif /*CONFIG_??MHz */
436 * For 16 MBit, refresh rates could be 31.3 us
437 * (= 64 ms / 2K = 125 / quad bursts).
438 * For a simpler initialization, 15.6 us is used instead.
440 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
441 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
443 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
444 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
446 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
447 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
448 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
451 * MAMR settings for SDRAM
455 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
456 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
457 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
459 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
460 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
461 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
463 #endif /* __CONFIG_H */