2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37 #define CONFIG_R360MPI 1
40 #undef CONFIG_EDT32F10
41 #define CONFIG_SHARP_LQ057Q3DC02
43 #define MPC8XX_FACT 1 /* Multiply by 1 */
44 #define MPC8XX_XIN 50000000 /* 50 MHz in */
45 #define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */
47 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
48 #undef CONFIG_8xx_CONS_SMC2
49 #undef CONFIG_8xx_CONS_NONE
50 #define CONFIG_BAUDRATE 115200 /* console baudrate in bps */
52 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
54 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
59 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
61 #undef CONFIG_BOOTARGS
62 #define CONFIG_BOOTCOMMAND \
64 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
65 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
68 #undef CONFIG_SCC1_ENET
69 #define CONFIG_SCC2_ENET
71 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
72 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
74 #define CONFIG_MISC_INIT_R /* have misc_init_r() function */
76 #undef CONFIG_WATCHDOG /* watchdog disabled */
80 # undef CONFIG_STATUS_LED /* disturbs display */
82 # define CONFIG_STATUS_LED 1 /* Status LED enabled */
83 #endif /* CONFIG_LCD */
86 #define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
88 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
90 #define CONFIG_MAC_PARTITION
91 #define CONFIG_DOS_PARTITION
93 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
95 #define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
96 #undef CONFIG_SORT_I2C /* To I2C with software support */
97 #define CFG_I2C_SPEED 4700 /* I2C speed and slave address */
98 #define CFG_I2C_SLAVE 0x7F
101 * Software (bit-bang) I2C driver configuration
103 #define PB_SCL 0x00000020 /* PB 26 */
104 #define PB_SDA 0x00000010 /* PB 27 */
106 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
107 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
108 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
109 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
110 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
111 else immr->im_cpm.cp_pbdat &= ~PB_SDA
112 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
113 else immr->im_cpm.cp_pbdat &= ~PB_SCL
114 #define I2C_DELAY udelay(50)
116 #define CFG_I2C_LCD_ADDR 0x8 /* LCD Control */
117 #define CFG_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
118 #define CFG_I2C_TEM_ADDR 0x49 /* Temperature Sensors */
120 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
128 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
129 #include <cmd_confdefs.h>
132 * Miscellaneous configurable options
134 #define CFG_LONGHELP /* undef to save memory */
135 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
136 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
137 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
139 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
141 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
142 #define CFG_MAXARGS 16 /* max number of command args */
143 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
145 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
146 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
148 #define CFG_LOAD_ADDR 0x100000 /* default load address */
150 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
152 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
155 * Low Level Configuration Settings
156 * (address mappings, register initial values, etc.)
157 * You should know what you are doing if you make changes here.
159 /*-----------------------------------------------------------------------
160 * Internal Memory Mapped Register
162 #define CFG_IMMR 0xFF000000
164 /*-----------------------------------------------------------------------
165 * Definitions for initial stack pointer and data area (in DPRAM)
167 #define CFG_INIT_RAM_ADDR CFG_IMMR
168 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
169 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
170 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
171 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
173 /*-----------------------------------------------------------------------
174 * Start addresses for the final memory configuration
175 * (Set up by the startup code)
176 * Please note that CFG_SDRAM_BASE _must_ start at 0
178 #define CFG_SDRAM_BASE 0x00000000
179 #define CFG_FLASH_BASE 0x40000000
181 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
183 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
185 #define CFG_MONITOR_BASE CFG_FLASH_BASE
186 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
189 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization.
193 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
195 /*-----------------------------------------------------------------------
198 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
199 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
201 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
202 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
204 #define CFG_ENV_IS_IN_FLASH 1
205 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */
206 #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
207 #define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
209 /*-----------------------------------------------------------------------
210 * Cache Configuration
212 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
213 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
214 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
217 /*-----------------------------------------------------------------------
218 * SYPCR - System Protection Control 11-9
219 * SYPCR can only be written once after reset!
220 *-----------------------------------------------------------------------
221 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
223 #if defined(CONFIG_WATCHDOG)
224 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
225 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
227 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
230 /*-----------------------------------------------------------------------
231 * SIUMCR - SIU Module Configuration 11-6
232 *-----------------------------------------------------------------------
233 * PCMCIA config., multi-function pin tri-state
235 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
237 /*-----------------------------------------------------------------------
238 * TBSCR - Time Base Status and Control 11-26
239 *-----------------------------------------------------------------------
240 * Clear Reference Interrupt Status, Timebase freezing enabled
242 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
244 /*-----------------------------------------------------------------------
245 * RTCSC - Real-Time Clock Status and Control Register 11-27
246 *-----------------------------------------------------------------------
248 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
250 /*-----------------------------------------------------------------------
251 * PISCR - Periodic Interrupt Status and Control 11-31
252 *-----------------------------------------------------------------------
253 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
255 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
257 /*-----------------------------------------------------------------------
258 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
259 *-----------------------------------------------------------------------
260 * Reset PLL lock status sticky bit, timer expired status bit and timer
261 * interrupt status bit
263 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
265 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
267 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
268 #else /* up to 50 MHz we use a 1:1 clock */
269 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
270 #endif /* CONFIG_80MHz */
272 /*-----------------------------------------------------------------------
273 * SCCR - System Clock and reset Control Register 15-27
274 *-----------------------------------------------------------------------
275 * Set clock output, timebase and RTC source and divider,
276 * power management and some other internal clocks
278 #define SCCR_MASK SCCR_EBDF11
279 #define CFG_SCCR (SCCR_TBS | \
280 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
281 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
284 /*-----------------------------------------------------------------------
286 *-----------------------------------------------------------------------
289 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
290 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
291 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
292 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
293 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
294 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
295 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
296 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
298 /*-----------------------------------------------------------------------
299 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
300 *-----------------------------------------------------------------------
304 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
306 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
307 #undef CONFIG_IDE_LED /* LED for ide not supported */
308 #undef CONFIG_IDE_RESET /* reset for ide not supported */
310 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
311 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
313 #define CFG_ATA_IDE0_OFFSET 0x0000
315 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
317 /* Offset for data I/O */
318 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
320 /* Offset for normal register accesses */
321 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
323 /* Offset for alternate registers */
324 #define CFG_ATA_ALT_OFFSET 0x0100
327 /*-----------------------------------------------------------------------
329 *-----------------------------------------------------------------------
332 #define CFG_DER 0x2002000F
333 /*#define CFG_DER 0*/
336 * Init Memory Controller:
338 * BR0/1 and OR0/1 (FLASH)
341 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
343 /* used to re-map FLASH both when starting from SRAM or FLASH:
344 * restrict access enough to keep SRAM working (if any)
345 * but not too much to meddle with FLASH accesses
347 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
348 #define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
353 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
355 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
356 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
357 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
361 * BR2 and OR2 (SDRAM)
364 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
365 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
367 #define CFG_PRELIM_OR2_AM 0xF8000000 /* OR addr mask */
369 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
370 #define CFG_OR_TIMING_SDRAM (OR_ACS_DIV1 | OR_CSNT_SAM | \
371 OR_SCY_0_CLK | OR_G5LS)
373 #define CFG_OR2_PRELIM (CFG_PRELIM_OR2_AM | CFG_OR_TIMING_SDRAM )
374 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
377 * BR3 and OR3 (CAN Controller)
379 #ifdef CONFIG_CAN_DRIVER
380 #define CFG_CAN_BASE 0xC0000000 /* CAN base address */
381 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
382 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA |OR_BI)
383 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
384 BR_PS_8 | BR_MS_UPMB | BR_V)
385 #endif /* CONFIG_CAN_DRIVER */
389 * Memory Periodic Timer Prescaler
391 * The Divider for PTA (refresh timer) configuration is based on an
392 * example SDRAM configuration (64 MBit, one bank). The adjustment to
393 * the number of chip selects (NCS) and the actually needed refresh
394 * rate is done by setting MPTPR.
396 * PTA is calculated from
397 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
399 * gclk CPU clock (not bus clock!)
400 * Trefresh Refresh cycle * 4 (four word bursts used)
402 * 4096 Rows from SDRAM example configuration
403 * 1000 factor s -> ms
404 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
405 * 4 Number of refresh cycles per period
406 * 64 Refresh cycle in ms per number of rows
407 * --------------------------------------------
408 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
410 * 50 MHz => 50.000.000 / Divider = 98
411 * 66 Mhz => 66.000.000 / Divider = 129
412 * 80 Mhz => 80.000.000 / Divider = 156
414 #if defined(CONFIG_80MHz)
415 #define CFG_MAMR_PTA 156
416 #elif defined(CONFIG_66MHz)
417 #define CFG_MAMR_PTA 129
419 #define CFG_MAMR_PTA 98
420 #endif /*CONFIG_??MHz */
423 * For 16 MBit, refresh rates could be 31.3 us
424 * (= 64 ms / 2K = 125 / quad bursts).
425 * For a simpler initialization, 15.6 us is used instead.
427 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
428 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
430 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
431 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
433 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
434 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
435 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
438 * MAMR settings for SDRAM
442 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
443 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
444 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
446 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
447 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
448 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
452 * Internal Definitions
456 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
457 #define BOOTFLAG_WARM 0x02 /* Software reboot */
459 #endif /* __CONFIG_H */