2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified by Udi Finkelstein udif@udif.com
6 * For the RBC823 board.
8 * SPDX-License-Identifier: GPL-2.0+
12 * board/config.h - configuration options, board specific
19 * High Level Configuration Options
23 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
24 #define CONFIG_RBC823 1 /* ...on a RBC823 module */
26 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
30 #define CONFIG_LAST_STAGE_INIT
32 #define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */
33 #define CONFIG_LCD 1 /* use LCD controller ... */
34 #define CONFIG_MPC8XX_LCD
35 #define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */
37 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
38 #undef CONFIG_8xx_CONS_SMC1
39 #undef CONFIG_8xx_CONS_NONE
40 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
42 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
44 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
48 #define CONFIG_8xx_GCLK_FREQ 48000000L
50 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
52 #undef CONFIG_BOOTARGS
53 #define CONFIG_BOOTCOMMAND \
55 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
56 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
59 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
60 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
62 #undef CONFIG_WATCHDOG /* watchdog disabled */
64 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
66 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
71 #define CONFIG_BOOTP_SUBNETMASK
72 #define CONFIG_BOOTP_GATEWAY
73 #define CONFIG_BOOTP_HOSTNAME
74 #define CONFIG_BOOTP_BOOTPATH
75 #define CONFIG_BOOTP_BOOTFILESIZE
78 #undef CONFIG_MAC_PARTITION
79 #define CONFIG_DOS_PARTITION
81 #undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */
83 #define CONFIG_HARD_I2C
84 #define CONFIG_SYS_I2C_SPEED 40000
85 #define CONFIG_SYS_I2C_SLAVE 0xfe
86 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
87 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
88 #define CONFIG_SYS_EEPROM_WRITE_BITS 4
89 #define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10
92 * Command line configuration.
94 #include <config_cmd_default.h>
96 #define CONFIG_CMD_ASKENV
97 #define CONFIG_CMD_BEDBUG
98 #define CONFIG_CMD_BMP
99 #define CONFIG_CMD_CACHE
100 #define CONFIG_CMD_CDP
101 #define CONFIG_CMD_DHCP
102 #define CONFIG_CMD_DIAG
103 #define CONFIG_CMD_EEPROM
104 #define CONFIG_CMD_ELF
105 #define CONFIG_CMD_FAT
106 #define CONFIG_CMD_I2C
107 #define CONFIG_CMD_IMMAP
108 #define CONFIG_CMD_KGDB
109 #define CONFIG_CMD_PING
110 #define CONFIG_CMD_PORTIO
111 #define CONFIG_CMD_REGINFO
112 #define CONFIG_CMD_SAVES
113 #define CONFIG_CMD_SDRAM
115 #undef CONFIG_CMD_SETGETDCR
116 #undef CONFIG_CMD_XIMG
119 * Miscellaneous configurable options
121 #define CONFIG_SYS_LONGHELP /* undef to save memory */
122 #if defined(CONFIG_CMD_KGDB)
123 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
125 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
127 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
128 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
129 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
131 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
132 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
134 #define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */
136 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
139 * Low Level Configuration Settings
140 * (address mappings, register initial values, etc.)
141 * You should know what you are doing if you make changes here.
143 /*-----------------------------------------------------------------------
144 * Internal Memory Mapped Register
146 #define CONFIG_SYS_IMMR 0xFF000000
148 /*-----------------------------------------------------------------------
149 * Definitions for initial stack pointer and data area (in DPRAM)
151 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
152 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
153 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
156 /*-----------------------------------------------------------------------
157 * Start addresses for the final memory configuration
158 * (Set up by the startup code)
159 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
161 #define CONFIG_SYS_SDRAM_BASE 0x00000000
162 #define CONFIG_SYS_FLASH_BASE 0xFFF00000
164 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */
166 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
169 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
172 * For booting Linux, the board info and command line data
173 * have to be in the first 8 MB of memory, since this is
174 * the maximum mapped by the Linux kernel during initialization.
176 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
178 /*-----------------------------------------------------------------------
181 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
182 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
184 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
185 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
187 #define CONFIG_ENV_IS_IN_FLASH 1
188 #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
189 #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
191 /*-----------------------------------------------------------------------
192 * Cache Configuration
194 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
195 #if defined(CONFIG_CMD_KGDB)
196 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
199 /*-----------------------------------------------------------------------
200 * SYPCR - System Protection Control 11-9
201 * SYPCR can only be written once after reset!
202 *-----------------------------------------------------------------------
203 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
205 #if defined(CONFIG_WATCHDOG)
206 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
207 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
210 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
212 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
215 /*-----------------------------------------------------------------------
216 * SIUMCR - SIU Module Configuration 11-6
217 *-----------------------------------------------------------------------
218 * PCMCIA config., multi-function pin tri-state
220 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
222 /*-----------------------------------------------------------------------
223 * TBSCR - Time Base Status and Control 11-26
224 *-----------------------------------------------------------------------
225 * Clear Reference Interrupt Status, Timebase freezing enabled
227 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
229 /*-----------------------------------------------------------------------
230 * RTCSC - Real-Time Clock Status and Control Register 11-27
231 *-----------------------------------------------------------------------
233 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
235 /*-----------------------------------------------------------------------
236 * PISCR - Periodic Interrupt Status and Control 11-31
237 *-----------------------------------------------------------------------
238 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
240 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
242 /*-----------------------------------------------------------------------
243 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
244 *-----------------------------------------------------------------------
245 * Reset PLL lock status sticky bit, timer expired status bit and timer
246 * interrupt status bit
251 * for 48 MHz, we use a 4 MHz clock * 12
253 #define CONFIG_SYS_PLPRCR \
254 ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
256 /*-----------------------------------------------------------------------
257 * SCCR - System Clock and reset Control Register 15-27
258 *-----------------------------------------------------------------------
259 * Set clock output, timebase and RTC source and divider,
260 * power management and some other internal clocks
262 #define SCCR_MASK SCCR_EBDF11
263 #define CONFIG_SYS_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \
264 SCCR_PRQEN | SCCR_EBDF00 | \
265 SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
266 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
270 /*-----------------------------------------------------------------------
272 *-----------------------------------------------------------------------
275 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
276 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
277 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
278 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
279 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
280 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
281 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
282 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
284 /*-----------------------------------------------------------------------
285 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
286 *-----------------------------------------------------------------------
289 #define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
291 #undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
292 #undef CONFIG_IDE_LED /* LED for ide not supported */
293 #undef CONFIG_IDE_RESET /* reset for ide not supported */
295 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
296 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
298 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
300 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
302 /* Offset for data I/O */
303 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
305 /* Offset for normal register accesses */
306 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
308 /* Offset for alternate registers */
309 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
313 /*-----------------------------------------------------------------------
315 *-----------------------------------------------------------------------
318 /*#define CONFIG_SYS_DER 0x2002000F*/
319 #define CONFIG_SYS_DER 0
322 * Init Memory Controller:
324 * BR0/1 and OR0/1 (FLASH)
327 #define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
328 #define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */
330 /* used to re-map FLASH both when starting from SRAM or FLASH:
331 * restrict access enough to keep SRAM working (if any)
332 * but not too much to meddle with FLASH accesses
334 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
336 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */
337 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
339 #define CONFIG_SYS_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI)
341 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
342 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
344 #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
345 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
349 * BR4 and OR4 (SDRAM)
352 #define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */
353 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
358 #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM)
360 #define CONFIG_SYS_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM )
361 #define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
364 * Memory Periodic Timer Prescaler
367 /* periodic timer for refresh */
368 #define CONFIG_SYS_MAMR_PTA 187 /* start with divider for 48 MHz */
370 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
371 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
372 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
374 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
375 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
376 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
379 * MAMR settings for SDRAM
383 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
384 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
385 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
387 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
388 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
389 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
395 /* No command line, one static partition, whole device */
396 #undef CONFIG_CMD_MTDPARTS
397 #define CONFIG_JFFS2_DEV "nor0"
398 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
399 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
401 /* mtdparts command line support */
402 /* Note: fake mtd_id used, no linux mtd map file */
404 #define CONFIG_CMD_MTDPARTS
405 #define MTDIDS_DEFAULT ""
406 #define MTDPARTS_DEFAULT ""
409 #endif /* __CONFIG_H */