2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
28 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
29 * U-Boot port on RPXlite board
35 #define RPXClassic_50MHz
38 * High Level Configuration Options
42 #define CONFIG_MPC860 1
43 #define CONFIG_RPXCLASSIC 1
45 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
46 #undef CONFIG_8xx_CONS_SMC2
47 #undef CONFIG_8xx_CONS_NONE
48 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
50 /* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */
51 #define CONFIG_FEC_ENET
52 #ifdef CONFIG_FEC_ENET
53 #define CFG_DISCOVER_PHY 1
55 #endif /* CONFIG_FEC_ENET */
57 /* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */
59 #define CONFIG_VIDEO_SED13806
60 #define CONFIG_NEC_NL6448BC20
61 #define CONFIG_VIDEO_SED13806_16BPP
63 #define CONFIG_CFB_CONSOLE
64 #define CONFIG_VIDEO_LOGO
65 #define CONFIG_VIDEO_BMP_LOGO
66 #define CONFIG_CONSOLE_EXTRA_INFO
67 #define CONFIG_VGA_AS_SINGLE_DEVICE
68 #define CONFIG_VIDEO_SW_CURSOR
72 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
74 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
77 #define CONFIG_ZERO_BOOTDELAY_CHECK 1
79 #undef CONFIG_BOOTARGS
80 #define CONFIG_BOOTCOMMAND \
82 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
83 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
86 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
87 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
89 #undef CONFIG_WATCHDOG /* watchdog disabled */
91 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
93 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
97 * Command line configuration.
99 #include <config_cmd_default.h>
101 #define CONFIG_CMD_ELF
105 * Miscellaneous configurable options
107 #define CFG_RESET_ADDRESS 0x80000000
108 #define CFG_LONGHELP /* undef to save memory */
109 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
110 #if defined(CONFIG_CMD_KGDB)
111 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
113 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
115 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
116 #define CFG_MAXARGS 16 /* max number of command args */
117 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
119 #define CFG_MEMTEST_START 0x0040000 /* memtest works on */
120 #define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
122 #define CFG_LOAD_ADDR 0x100000 /* default load address */
124 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
126 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
129 * Low Level Configuration Settings
130 * (address mappings, register initial values, etc.)
131 * You should know what you are doing if you make changes here.
133 /*-----------------------------------------------------------------------
134 * Internal Memory Mapped Register
136 #define CFG_IMMR 0xFA200000
138 /*-----------------------------------------------------------------------------
140 *-----------------------------------------------------------------------------
143 #define CFG_I2C_SPEED 50000
144 #define CFG_I2C_SLAVE 0x34
147 /* enable I2C and select the hardware/software driver */
148 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
149 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
151 * Software (bit-bang) I2C driver configuration
153 #define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */
154 #define I2C_ACTIVE (iop->pdir |= 0x00000010)
155 #define I2C_TRISTATE (iop->pdir &= ~0x00000010)
156 #define I2C_READ ((iop->pdat & 0x00000010) != 0)
157 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \
158 else iop->pdat &= ~0x00000010
159 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \
160 else iop->pdat &= ~0x00000020
161 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
164 # define CFG_I2C_SPEED 50000
165 # define CFG_I2C_SLAVE 0x34
166 # define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
167 # define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
168 /* mask of address bits that overflow into the "EEPROM chip address" */
169 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
171 /*-----------------------------------------------------------------------
172 * Definitions for initial stack pointer and data area (in DPRAM)
174 #define CFG_INIT_RAM_ADDR CFG_IMMR
175 #define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
176 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
177 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
178 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
180 /*-----------------------------------------------------------------------
181 * Start addresses for the final memory configuration
182 * (Set up by the startup code)
183 * Please note that CFG_SDRAM_BASE _must_ start at 0
185 #define CFG_SDRAM_BASE 0x00000000
186 #define CFG_FLASH_BASE 0xFF000000
188 #if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE)
189 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
191 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
193 #define CFG_MONITOR_BASE 0xFF000000
194 /*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
195 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization.
202 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
204 /*-----------------------------------------------------------------------
207 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
208 #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
210 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
211 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
214 #define CFG_ENV_IS_IN_FLASH 1
215 #define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
216 #define CFG_ENV_SECT_SIZE 0x8000
217 #define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
219 #define CFG_ENV_IS_IN_NVRAM 1
220 #define CFG_ENV_ADDR 0xfa000100
221 #define CFG_ENV_SIZE 0x1000
224 /*-----------------------------------------------------------------------
225 * Cache Configuration
227 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
228 #if defined(CONFIG_CMD_KGDB)
229 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
232 /*-----------------------------------------------------------------------
233 * SYPCR - System Protection Control 11-9
234 * SYPCR can only be written once after reset!
235 *-----------------------------------------------------------------------
236 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
238 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
241 /*-----------------------------------------------------------------------
242 * SIUMCR - SIU Module Configuration 11-6
243 *-----------------------------------------------------------------------
244 * PCMCIA config., multi-function pin tri-state
246 #define CFG_SIUMCR (SIUMCR_MLRC10)
248 /*-----------------------------------------------------------------------
249 * TBSCR - Time Base Status and Control 11-26
250 *-----------------------------------------------------------------------
251 * Clear Reference Interrupt Status, Timebase freezing enabled
253 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
255 /*-----------------------------------------------------------------------
256 * RTCSC - Real-Time Clock Status and Control Register 11-27
257 *-----------------------------------------------------------------------
259 /*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
260 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE)
262 /*-----------------------------------------------------------------------
263 * PISCR - Periodic Interrupt Status and Control 11-31
264 *-----------------------------------------------------------------------
265 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
267 #define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
269 /*-----------------------------------------------------------------------
270 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
271 *-----------------------------------------------------------------------
272 * Reset PLL lock status sticky bit, timer expired status bit and timer
273 * interrupt status bit
275 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
277 /* up to 50 MHz we use a 1:1 clock */
278 #define CFG_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
280 /*-----------------------------------------------------------------------
281 * SCCR - System Clock and reset Control Register 15-27
282 *-----------------------------------------------------------------------
283 * Set clock output, timebase and RTC source and divider,
284 * power management and some other internal clocks
286 #define SCCR_MASK SCCR_EBDF00
287 /* up to 50 MHz we use a 1:1 clock */
288 #define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
290 /*-----------------------------------------------------------------------
292 *-----------------------------------------------------------------------
295 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
296 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
297 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
298 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
299 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
300 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
301 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
302 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
304 /*-----------------------------------------------------------------------
305 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
306 *-----------------------------------------------------------------------
309 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
311 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
312 #undef CONFIG_IDE_LED /* LED for ide not supported */
313 #undef CONFIG_IDE_RESET /* reset for ide not supported */
315 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
316 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
318 #define CFG_ATA_IDE0_OFFSET 0x0000
320 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
322 /* Offset for data I/O */
323 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
325 /* Offset for normal register accesses */
326 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
328 /* Offset for alternate registers */
329 #define CFG_ATA_ALT_OFFSET 0x0100
331 /*-----------------------------------------------------------------------
333 *-----------------------------------------------------------------------
336 /* #define CFG_DER 0x2002000F */
340 * Init Memory Controller:
342 * BR0 and OR0 (FLASH)
345 #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
346 #define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
348 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
349 #define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
351 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
352 #define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
355 * BR1 and OR1 (SDRAM)
358 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
359 #define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
361 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
362 #define CFG_OR_TIMING_SDRAM 0x00000E00
364 #define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
365 #define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
367 /* RPXLITE mem setting */
368 #define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
369 #define CFG_OR3_PRELIM 0xff7f8970
370 #define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
371 #define CFG_OR4_PRELIM 0xFFF80970
373 /* ECCX CS settings */
374 #define SED13806_OR 0xFFC00108 /* - 4 Mo
377 #define SED13806_REG_ADDR 0xa0000000
378 #define SED13806_ACCES 0x801 /* 16 bit access */
381 /* Global definitions for the ECCX board */
382 #define ECCX_CSR_ADDR (0xfac00000)
383 #define ECCX_CSR8_OFFSET (0x8)
384 #define ECCX_CSR11_OFFSET (0xB)
385 #define ECCX_CSR12_OFFSET (0xC)
387 #define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
388 #define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
389 #define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
392 #define REG_GPIO_CTRL 0x008
394 /* Definitions for CSR8 */
395 #define ECCX_ENEPSON 0x80 /* Bit 0:
396 0= disable and reset SED1386
398 /* Bit 1: 0= SED1386 in Big Endian mode */
399 /* 1= SED1386 in little endian mode */
403 /* Bit 2,3: Selection */
405 /* 01 = CS2 is used for the SED1386 */
406 /* 10 = CS5 is used for the SED1386 */
408 #define ECCX_CS2 0x10
409 #define ECCX_CS5 0x20
411 /* Definitions for CSR12 */
413 #define ECCX_860 0x01
416 * Memory Periodic Timer Prescaler
419 /* periodic timer for refresh */
420 #define CFG_MAMR_PTA 58
423 * Refresh clock Prescalar
425 #define CFG_MPTPR MPTPR_PTP_DIV8
428 * MAMR settings for SDRAM
431 /* 10 column SDRAM */
432 #define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
433 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
434 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
437 * Internal Definitions
441 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
442 #define BOOTFLAG_WARM 0x02 /* Software reboot */
445 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
446 /* Configuration variable added by yooth. */
447 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
452 * Board Status and Control Registers
456 #define BCSR0 0xFA400000
457 #define BCSR1 0xFA400001
458 #define BCSR2 0xFA400002
459 #define BCSR3 0xFA400003
461 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
462 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
463 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
464 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
465 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
466 #define BCSR0_COLTEST 0x20
467 #define BCSR0_ETHLPBK 0x40
468 #define BCSR0_ETHEN 0x80
470 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
471 #define BCSR1_PCVCTL6 0x02
472 #define BCSR1_PCVCTL5 0x04
473 #define BCSR1_PCVCTL4 0x08
474 #define BCSR1_IPB5SEL 0x10
476 #define BCSR2_MIIRST 0x80
477 #define BCSR2_MIIPWRDWN 0x40
478 #define BCSR2_MIICTL 0x08
480 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
481 #define BCSR3_BWNVR 0x02 /* NVRAM Battery */
482 #define BCSR3_RDY_BSY 0x04 /* Flash Operation */
483 #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
484 #define BCSR3_D27 0x10 /* Dip Switch settings */
485 #define BCSR3_D26 0x20
486 #define BCSR3_D25 0x40
487 #define BCSR3_D24 0x80
491 * Environment setting
494 /* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */
495 /* #define CONFIG_IPADDR 10.10.106.1 */
496 /* #define CONFIG_SERVERIP 10.10.104.11 */
498 #endif /* __CONFIG_H */