2 * Copyright (C) Sheldon Instruments, Inc. 2008
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * simpc8313 board configuration file
30 * High Level Configuration Options
32 #define CONFIG_NAND_U_BOOT
35 #define CONFIG_MPC83xx 1
36 #define CONFIG_MPC831x 1
37 #define CONFIG_MPC8313 1
39 #ifndef CONFIG_SYS_TEXT_BASE
40 #define CONFIG_SYS_TEXT_BASE 0x00100000
44 #define CONFIG_FSL_ELBC 1
46 #define CONFIG_MISC_INIT_R
51 * TSEC1 is Marvell PHY 88E1118
54 #define CONFIG_SYS_33MHZ
56 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
58 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
60 #define CONFIG_SYS_IMMR 0xE0000000
62 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
63 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
66 #define CONFIG_SYS_MEMTEST_START 0x00001000
67 #define CONFIG_SYS_MEMTEST_END 0x07f00000
69 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
70 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
73 * Device configurations
80 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
81 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
82 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
84 #define CONFIG_VERY_BIG_RAM
85 #define CONFIG_MAX_MEM_MAPPED (512 << 20)
87 #define CONFIG_SYS_DDRCDR ( DDRCDR_EN \
91 /* 0x73000002 TODO ODR & DRN ? */
94 * FLASH on the Local Bus
96 #define CONFIG_SYS_NO_FLASH
98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
100 #if !defined(CONFIG_NAND_SPL)
101 #define CONFIG_SYS_RAMBOOT
104 #define CONFIG_SYS_INIT_RAM_LOCK 1
105 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
106 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
108 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
109 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
111 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
112 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
113 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
116 * Local Bus LCRR and LBCR regs
118 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
119 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
120 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
121 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
122 | (0xFF << LBCR_BMT_SHIFT) \
123 | 0xF ) /* 0x0004ff0f */
125 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
127 /* drivers/mtd/nand/nand.c */
128 #ifdef CONFIG_NAND_SPL
129 #define CONFIG_SYS_NAND_BASE 0xFFF00000
131 #define CONFIG_SYS_NAND_BASE 0xE2800000
133 #define CONFIG_SYS_FPGA_BASE 0xFF000000
135 #define CONFIG_SYS_MAX_NAND_DEVICE 1
136 #define NAND_MAX_CHIPS 1
137 #define CONFIG_MTD_NAND_VERIFY_WRITE
138 #define CONFIG_CMD_NAND 1
139 #define CONFIG_NAND_FSL_ELBC 1
141 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
142 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
143 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
144 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
145 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
147 #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
148 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
149 | BR_PS_8 /* Port Size = 8 bit */ \
150 | BR_MS_FCM /* MSEL = FCM */ \
153 #ifdef CONFIG_NAND_SP
154 #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
161 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
162 #define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
163 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
164 #define NAND_CACHE_PAGES 32
165 #elif defined(CONFIG_NAND_LP)
166 #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \
174 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
175 #define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
176 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
177 #define NAND_CACHE_PAGES 64
179 #error Page size of NAND not defined.
180 #endif /* CONFIG_NAND_SP */
182 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
184 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
185 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
187 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
189 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
190 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
192 #define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_FPGA_BASE \
196 #define CONFIG_SYS_OR1_PRELIM ( OR_AM_2MB \
199 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
200 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB)
203 * JFFS2 configuration
205 #define CONFIG_JFFS2_NAND
206 #define CONFIG_JFFS2_DEV "nand0"
208 /* mtdparts command line support */
209 #define CONFIG_CMD_MTDPARTS
210 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
211 #define MTDIDS_DEFAULT "nand0=nand0"
212 #define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
214 /* pass open firmware flat tree */
215 #define CONFIG_OF_LIBFDT 1
216 #define CONFIG_OF_BOARD_SETUP 1
217 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
222 #define CONFIG_CONS_INDEX 1
223 #define CONFIG_SYS_NS16550
224 #define CONFIG_SYS_NS16550_SERIAL
225 #define CONFIG_SYS_NS16550_REG_SIZE 1
226 #ifdef CONFIG_NAND_SPL
227 #define CONFIG_NS16550_MIN_FUNCTIONS
230 #define CONFIG_SYS_BAUDRATE_TABLE \
231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
233 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
234 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
236 /* Use the HUSH parser */
237 #define CONFIG_SYS_HUSH_PARSER
238 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
241 #define CONFIG_HARD_I2C /* I2C with hardware support*/
242 #define CONFIG_FSL_I2C
243 #define CONFIG_I2C_MULTI_BUS
244 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
245 #define CONFIG_SYS_I2C_SLAVE 0x7F
246 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
247 #define CONFIG_SYS_I2C_OFFSET 0x3000
248 #define CONFIG_SYS_I2C2_OFFSET 0x3100
252 * Addresses are mapped 1-1.
254 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
255 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
256 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
257 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
258 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
259 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
260 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
261 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
262 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
264 #define CONFIG_PCI_PNP /* do pci plug-and-play */
265 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
270 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
272 #define CONFIG_NET_MULTI
273 #define CONFIG_GMII /* MII PHY management */
276 #define CONFIG_HAS_ETH0
277 #define CONFIG_TSEC1_NAME "TSEC0"
278 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
279 #define TSEC1_PHY_ADDR 0x0
280 #define TSEC1_FLAGS TSEC_GIGABIT
281 #define TSEC1_PHYIDX 0
285 #define CONFIG_HAS_ETH1
286 #define CONFIG_TSEC2_NAME "TSEC1"
287 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
288 #define TSEC2_PHY_ADDR 4
289 #define TSEC2_FLAGS TSEC_GIGABIT
290 #define TSEC2_PHYIDX 0
294 /* Options are: TSEC[0-1] */
295 #define CONFIG_ETHPRIME "TSEC1"
298 * Configure on-board RTC
300 #define CONFIG_RTC_DS1337
301 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
306 #if defined(CONFIG_NAND_U_BOOT)
307 #define CONFIG_ENV_IS_IN_NAND 1
308 #define CONFIG_ENV_OFFSET (768 * 1024)
309 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
310 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
311 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
312 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
313 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
314 #elif !defined(CONFIG_SYS_RAMBOOT)
315 #define CONFIG_ENV_IS_IN_FLASH 1
316 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
317 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
318 #define CONFIG_ENV_SIZE 0x2000
320 /* Address and size of Redundant Environment Sector */
322 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
323 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
324 #define CONFIG_ENV_SIZE 0x2000
327 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
328 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
333 #define CONFIG_BOOTP_BOOTFILESIZE
334 #define CONFIG_BOOTP_BOOTPATH
335 #define CONFIG_BOOTP_GATEWAY
336 #define CONFIG_BOOTP_HOSTNAME
340 * Command line configuration.
342 #include <config_cmd_default.h>
343 #undef CONFIG_CMD_IMLS
344 #undef CONFIG_CMD_FLASH
346 #define CONFIG_CMD_PING
347 #define CONFIG_CMD_DHCP
348 #define CONFIG_CMD_I2C
349 #define CONFIG_CMD_MII
350 #define CONFIG_CMD_DATE
351 #define CONFIG_CMD_PCI
352 #define CONFIG_CMD_JFFS2
354 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
355 #undef CONFIG_CMD_SAVEENV
356 #undef CONFIG_CMD_LOADS
359 #define CONFIG_CMDLINE_EDITING 1
360 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
363 * Miscellaneous configurable options
365 #define CONFIG_SYS_LONGHELP /* undef to save memory */
366 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
367 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
368 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
370 #define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \
371 + sizeof(CONFIG_SYS_PROMPT) \
372 + 16 ) /* Print Buffer Size */
373 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
374 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
375 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
378 * For booting Linux, the board info and command line data
379 * have to be in the first 256 MB of memory, since this is
380 * the maximum mapped by the Linux kernel during initialization.
382 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
384 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
386 #define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
387 | 0x20000000 /* reserved */ \
388 | HRCWL_DDR_TO_SCB_CLK_2X1 \
389 | HRCWL_CSB_TO_CLKIN_4X1 \
390 | HRCWL_CORE_TO_CSB_2_5X1 )
392 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
394 #define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \
395 | HRCWH_PCI1_ARBITER_ENABLE \
396 | HRCWH_CORE_ENABLE \
397 | HRCWH_BOOTSEQ_DISABLE \
398 | HRCWH_SW_WATCHDOG_DISABLE \
399 | HRCWH_TSEC1M_IN_RGMII \
400 | HRCWH_TSEC2M_IN_RGMII \
402 | HRCWH_LALE_NORMAL )
404 #ifdef CONFIG_NAND_LP
405 #define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
406 | HRCWH_FROM_0XFFF00100 \
407 | HRCWH_ROM_LOC_NAND_LP_8BIT \
410 #define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
411 | HRCWH_FROM_0XFFF00100 \
412 | HRCWH_ROM_LOC_NAND_SP_8BIT \
413 | HRCWH_RL_EXT_NAND )
416 /* System IO Config */
417 #define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \
425 #define CONFIG_SYS_SICRL ( SICRL_LBC \
429 #define CONFIG_SYS_HID0_INIT 0x000000000
430 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
431 HID0_ENABLE_INSTRUCTION_CACHE | \
432 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
434 #define CONFIG_SYS_HID2 HID2_HBE
436 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
438 /* DDR @ 0x00000000 */
439 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
440 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
441 #define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
442 #define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
444 /* PCI @ 0x80000000 */
445 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
446 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
447 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
448 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
450 /* PCI2 not supported on 8313 */
451 #define CONFIG_SYS_IBAT4L (0)
452 #define CONFIG_SYS_IBAT4U (0)
454 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
455 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
456 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
458 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
459 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
460 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
462 #define CONFIG_SYS_IBAT7L (0)
463 #define CONFIG_SYS_IBAT7U (0)
465 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
466 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
467 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
468 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
469 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
470 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
471 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
472 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
473 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
474 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
475 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
476 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
477 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
478 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
479 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
480 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
483 * Environment Configuration
485 #define CONFIG_ENV_OVERWRITE
487 #define CONFIG_NETDEV eth1
489 #define CONFIG_HOSTNAME simpc8313
490 #define CONFIG_ROOTPATH /tftpboot/
491 #define CONFIG_BOOTFILE /tftpboot/uImage
492 #define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */
493 #define CONFIG_FDTFILE simpc8313.dtb
495 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
496 #define CONFIG_BOOTDELAY 5 /* 5 second delay */
497 #define CONFIG_BAUDRATE 115200
499 #define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
501 #define XMK_STR(x) #x
502 #define MK_STR(x) XMK_STR(x)
504 #define CONFIG_EXTRA_ENV_SETTINGS \
505 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
507 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
508 "tftpflash=tftpboot $loadaddr $uboot; " \
509 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
510 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
511 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
512 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
513 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
515 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
517 "setbootargs=setenv bootargs " \
518 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
519 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
520 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
521 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
522 "load_uboot=tftp 100000 u-boot-nand.bin\0" \
523 "burn_uboot=nand erase u-boot 80000; " \
524 "nand write 100000 u-boot $filesize\0" \
525 "update_uboot=run load_uboot;run burn_uboot\0" \
526 "mtdids=nand0=nand0\0" \
527 "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
528 "nfsargs=setenv bootargs root=/dev/nfs rw " \
529 "nfsroot=${serverip}:${rootpath}\0" \
530 "ramargs=setenv bootargs root=/dev/ram rw\0" \
531 "addip=setenv bootargs ${bootargs} " \
532 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
533 ":${hostname}:${netdev}:off panic=1\0" \
534 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
535 "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
536 "console=ttyS0,115200\0" \
539 #define CONFIG_NFSBOOTCOMMAND \
540 "setenv rootdev /dev/nfs;" \
543 "tftp $loadaddr $bootfile;" \
544 "tftp $fdtaddr $fdtfile;" \
545 "bootm $loadaddr - $fdtaddr"
547 #define CONFIG_RAMBOOTCOMMAND \
548 "setenv rootdev /dev/ram;" \
550 "tftp $ramdiskaddr $ramdiskfile;" \
551 "tftp $loadaddr $bootfile;" \
552 "tftp $fdtaddr $fdtfile;" \
553 "bootm $loadaddr $ramdiskaddr $fdtaddr"
558 #endif /* __CONFIG_H */