2 * U-Boot configuration for SIXNET SXNI855T CPU board.
3 * This board is based (loosely) on the Motorola FADS board, so this
4 * file is based (loosely) on config_FADS860T.h, see it for additional
7 * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * ff100000 -> ff13ffff : FPGA CS1
33 * ff030000 -> ff03ffff : EXPANSION CS7
34 * ff020000 -> ff02ffff : DATA FLASH CS4
35 * ff018000 -> ff01ffff : UART B CS6/UPMB
36 * ff010000 -> ff017fff : UART A CS5/UPMB
37 * ff000000 -> ff00ffff : IMAP internal to the MPC855T
38 * f8000000 -> fbffffff : FLASH CS0 up to 64MB
39 * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB
40 * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB
43 /* ------------------------------------------------------------------------- */
46 * board/config.h - configuration options, board specific
53 * High Level Configuration Options
56 #include <mpc8xx_irq.h>
58 #define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */
60 /* The 855T is just a stripped 860T and needs code for 860, so for now
61 * at least define 860, 860T and 855T
63 #define CONFIG_MPC860 1
64 #define CONFIG_MPC860T 1
65 #define CONFIG_MPC855T 1
67 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
68 #undef CONFIG_8xx_CONS_SMC2
69 #undef CONFIG_8xx_CONS_SCC1
70 #undef CONFIG_8xx_CONS_NONE
71 #define CONFIG_BAUDRATE 9600
72 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
74 #define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */
76 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
79 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
81 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
84 #define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */
85 #define CONFIG_BOOTARGS "root=/dev/ram ip=off"
87 #define CONFIG_MISC_INIT_R /* have misc_init_r() function */
88 #define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
90 #undef CONFIG_WATCHDOG /* watchdog disabled */
92 #define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */
94 #define CONFIG_SOFT_I2C /* I2C bit-banged */
96 * Software (bit-bang) I2C driver configuration
98 #define PB_SCL 0x00000020 /* PB 26 */
99 #define PB_SDA 0x00000010 /* PB 27 */
101 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
102 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
103 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
104 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
105 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
106 else immr->im_cpm.cp_pbdat &= ~PB_SDA
107 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
108 else immr->im_cpm.cp_pbdat &= ~PB_SCL
109 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
111 # define CFG_I2C_SPEED 50000
112 # define CFG_I2C_SLAVE 0xFE
113 # define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */
114 # define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
116 #define CONFIG_FEC_ENET 1 /* use FEC ethernet */
118 #define CFG_DISCOVER_PHY
120 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM | CFG_CMD_DATE)
122 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
123 #include <cmd_confdefs.h>
126 * Miscellaneous configurable options
128 #define CFG_LONGHELP /* undef to save a little memory */
129 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
130 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
131 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
133 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
135 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
136 #define CFG_MAXARGS 16 /* max number of command args */
137 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
139 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
140 #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
142 #define CFG_LOAD_ADDR 0x00100000
144 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
146 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
149 * Low Level Configuration Settings
150 * (address mappings, register initial values, etc.)
151 * You should know what you are doing if you make changes here.
153 /*-----------------------------------------------------------------------
154 * Internal Memory Mapped Register
156 #define CFG_IMMR 0xFF000000
157 #define CFG_IMMR_SIZE ((uint)(64 * 1024))
159 /*-----------------------------------------------------------------------
160 * Definitions for initial stack pointer and data area (in DPRAM)
162 #define CFG_INIT_RAM_ADDR CFG_IMMR
163 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
164 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
165 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
166 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
168 /*-----------------------------------------------------------------------
169 * Start addresses for the final memory configuration
170 * (Set up by the startup code)
171 * Please note that CFG_SDRAM_BASE _must_ start at 0
173 #define CFG_SDRAM_BASE 0x00000000
174 #define CFG_SRAM_BASE 0xF4000000
175 #define CFG_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */
177 #define CFG_FLASH_BASE 0xF8000000
178 #define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
180 #define CFG_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */
181 #define CFG_DFLASH_SIZE 0x00010000
183 #define CFG_FPGA_BASE 0xFF100000 /* Xilinx FPGA */
184 #define CFG_FPGA_PROG 0xFF130000 /* Programming address */
185 #define CFG_FPGA_SIZE 0x00040000 /* 256KiB usable */
187 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
188 #define CFG_MONITOR_BASE CFG_FLASH_BASE
189 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
192 * For booting Linux, the board info and command line data
193 * have to be in the first 8 MB of memory, since this is
194 * the maximum mapped by the Linux kernel during initialization.
196 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
197 /*-----------------------------------------------------------------------
200 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
201 /* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
202 * AMD 29LV641 has 128 64K sectors in 8MB
204 #define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
206 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
207 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
209 /*-----------------------------------------------------------------------
210 * Cache Configuration
212 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
213 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
214 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
217 /*-----------------------------------------------------------------------
218 * SYPCR - System Protection Control 11-9
219 * SYPCR can only be written once after reset!
220 *-----------------------------------------------------------------------
221 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
223 #if defined(CONFIG_WATCHDOG)
224 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
225 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
227 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
230 /*-----------------------------------------------------------------------
231 * SIUMCR - SIU Module Configuration 11-6
232 *-----------------------------------------------------------------------
233 * PCMCIA config., multi-function pin tri-state
235 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
237 /*-----------------------------------------------------------------------
238 * TBSCR - Time Base Status and Control 11-26
239 *-----------------------------------------------------------------------
240 * Clear Reference Interrupt Status, Timebase freezing enabled
242 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
244 /*-----------------------------------------------------------------------
245 * PISCR - Periodic Interrupt Status and Control 11-31
246 *-----------------------------------------------------------------------
247 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
249 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
251 /*-----------------------------------------------------------------------
252 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
253 *-----------------------------------------------------------------------
254 * set the PLL, the low-power modes and the reset control (15-29)
256 #define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
257 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
259 /*-----------------------------------------------------------------------
260 * SCCR - System Clock and reset Control Register 15-27
261 *-----------------------------------------------------------------------
262 * Set clock output, timebase and RTC source and divider,
263 * power management and some other internal clocks
265 #define SCCR_MASK SCCR_EBDF11
266 #define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
268 /*-----------------------------------------------------------------------
270 *-----------------------------------------------------------------------
275 /* Because of the way the 860 starts up and assigns CS0 the
276 * entire address space, we have to set the memory controller
277 * differently. Normally, you write the option register
278 * first, and then enable the chip select by writing the
279 * base register. For CS0, you must write the base register
280 * first, followed by the option register.
284 * Init Memory Controller:
286 **********************************************************
287 * BR0 and OR0 (FLASH)
290 #define CFG_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */
292 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
293 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
295 #define CFG_OR0_PRELIM (CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH)
297 #define CONFIG_FLASH_16BIT
298 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
299 #define CFG_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */
301 /**********************************************************
303 * These preliminary values are also the final values.
305 #define CFG_OR_TIMING_FPGA \
306 (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
307 #define CFG_BR1_PRELIM ((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
308 #define CFG_OR1_PRELIM (((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA)
310 /**********************************************************
311 * BR4 and OR4 (data flash)
312 * These preliminary values are also the final values.
314 #define CFG_OR_TIMING_DFLASH \
315 (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
316 #define CFG_BR4_PRELIM ((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
317 #define CFG_OR4_PRELIM (((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH)
319 /**********************************************************
320 * BR5/6 and OR5/6 (Dual UART)
322 #define CFG_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */
323 #define CFG_DUARTA_BASE 0xff010000
324 #define CFG_DUARTB_BASE 0xff018000
327 #define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI)
328 #define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
329 #define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
330 #define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
332 /**********************************************************
336 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
337 #define BOOTFLAG_WARM 0x02 /* Software reboot */
339 #define CONFIG_RESET_ON_PANIC /* reset if system panic() */
341 /* to put environment in EEROM */
342 #define CFG_ENV_IS_IN_EEPROM 1
343 #define CFG_ENV_OFFSET 0 /* Start right at beginning of NVRAM */
344 #define CFG_ENV_SIZE 1024 /* Use only a part of it*/
347 #define CONFIG_BOOT_RETRY_TIME 60 /* boot if no command in 60 seconds */
351 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
352 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
353 #define CONFIG_AUTOBOOT_DELAY_STR "delayabit"
354 #define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */
357 #endif /* __CONFIG_H */