2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T1024/T1023 QDS board configuration file
14 /* High Level Configuration Options */
15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
16 #define CONFIG_MP /* support multiple processors */
17 #define CONFIG_ENABLE_36BIT_PHYS
19 #ifdef CONFIG_PHYS_64BIT
20 #define CONFIG_ADDR_MAP 1
21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
27 #define CONFIG_ENV_OVERWRITE
29 #define CONFIG_DEEP_SLEEP
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
33 #define CONFIG_SPL_FLUSH_IMAGE
34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
35 #define CONFIG_SYS_TEXT_BASE 0x00201000
36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
37 #define CONFIG_SPL_PAD_TO 0x40000
38 #define CONFIG_SPL_MAX_SIZE 0x28000
39 #define RESET_VECTOR_OFFSET 0x27FFC
40 #define BOOT_PAGE_OFFSET 0x27000
41 #ifdef CONFIG_SPL_BUILD
42 #define CONFIG_SPL_SKIP_RELOCATE
43 #define CONFIG_SPL_COMMON_INIT_DDR
44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
50 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
54 #define CONFIG_SPL_NAND_BOOT
57 #ifdef CONFIG_SPIFLASH
58 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
59 #define CONFIG_SPL_SPI_FLASH_MINIMAL
60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
64 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
65 #ifndef CONFIG_SPL_BUILD
66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
69 #define CONFIG_SPL_SPI_BOOT
73 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
74 #define CONFIG_SPL_MMC_MINIMAL
75 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
76 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
77 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
78 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
80 #ifndef CONFIG_SPL_BUILD
81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
83 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
84 #define CONFIG_SPL_MMC_BOOT
87 #endif /* CONFIG_RAMBOOT_PBL */
89 #ifndef CONFIG_SYS_TEXT_BASE
90 #define CONFIG_SYS_TEXT_BASE 0xeff40000
93 #ifndef CONFIG_RESET_VECTOR_ADDRESS
94 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
97 #ifdef CONFIG_MTD_NOR_FLASH
98 #define CONFIG_FLASH_CFI_DRIVER
99 #define CONFIG_SYS_FLASH_CFI
100 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
103 /* PCIe Boot - Master */
104 #define CONFIG_SRIO_PCIE_BOOT_MASTER
106 * for slave u-boot IMAGE instored in master memory space,
107 * PHYS must be aligned based on the SIZE
109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
111 #ifdef CONFIG_PHYS_64BIT
112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
119 * for slave UCODE and ENV instored in master memory space,
120 * PHYS must be aligned based on the SIZE
122 #ifdef CONFIG_PHYS_64BIT
123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
124 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
130 /* slave core release by master*/
131 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
132 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
134 /* PCIe Boot - Slave */
135 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
136 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
137 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
138 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
139 /* Set 1M boot space for PCIe boot */
140 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
141 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
142 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
143 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
146 #if defined(CONFIG_SPIFLASH)
147 #define CONFIG_SYS_EXTRA_ENV_RELOC
148 #define CONFIG_ENV_IS_IN_SPI_FLASH
149 #define CONFIG_ENV_SPI_BUS 0
150 #define CONFIG_ENV_SPI_CS 0
151 #define CONFIG_ENV_SPI_MAX_HZ 10000000
152 #define CONFIG_ENV_SPI_MODE 0
153 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
154 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
155 #define CONFIG_ENV_SECT_SIZE 0x10000
156 #elif defined(CONFIG_SDCARD)
157 #define CONFIG_SYS_EXTRA_ENV_RELOC
158 #define CONFIG_SYS_MMC_ENV_DEV 0
159 #define CONFIG_ENV_SIZE 0x2000
160 #define CONFIG_ENV_OFFSET (512 * 0x800)
161 #elif defined(CONFIG_NAND)
162 #define CONFIG_SYS_EXTRA_ENV_RELOC
163 #define CONFIG_ENV_SIZE 0x2000
164 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
165 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
166 #define CONFIG_ENV_IS_IN_REMOTE
167 #define CONFIG_ENV_ADDR 0xffe20000
168 #define CONFIG_ENV_SIZE 0x2000
169 #elif defined(CONFIG_ENV_IS_NOWHERE)
170 #define CONFIG_ENV_SIZE 0x2000
172 #define CONFIG_ENV_IS_IN_FLASH
173 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
174 #define CONFIG_ENV_SIZE 0x2000
175 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
179 unsigned long get_board_sys_clk(void);
180 unsigned long get_board_ddr_clk(void);
183 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
184 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
187 * These can be toggled for performance analysis, otherwise use default.
189 #define CONFIG_SYS_CACHE_STASHING
190 #define CONFIG_BACKSIDE_L2_CACHE
191 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
192 #define CONFIG_BTB /* toggle branch predition */
193 #define CONFIG_DDR_ECC
194 #ifdef CONFIG_DDR_ECC
195 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
196 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
199 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
200 #define CONFIG_SYS_MEMTEST_END 0x00400000
201 #define CONFIG_SYS_ALT_MEMTEST
202 #define CONFIG_PANIC_HANG /* do not reset board on panic */
205 * Config the L3 Cache as L3 SRAM
207 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
208 #define CONFIG_SYS_L3_SIZE (256 << 10)
209 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
210 #ifdef CONFIG_RAMBOOT_PBL
211 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
213 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
214 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
215 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
216 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
218 #ifdef CONFIG_PHYS_64BIT
219 #define CONFIG_SYS_DCSRBAR 0xf0000000
220 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
224 #define CONFIG_ID_EEPROM
225 #define CONFIG_SYS_I2C_EEPROM_NXID
226 #define CONFIG_SYS_EEPROM_BUS_NUM 0
227 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
228 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
235 #define CONFIG_VERY_BIG_RAM
236 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
237 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
238 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
239 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
240 #define CONFIG_DDR_SPD
242 #define CONFIG_SYS_SPD_BUS_NUM 0
243 #define SPD_EEPROM_ADDRESS 0x51
245 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
250 #define CONFIG_SYS_FLASH_BASE 0xe0000000
251 #ifdef CONFIG_PHYS_64BIT
252 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
254 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
257 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
258 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
260 CSPR_PORT_SIZE_16 | \
263 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
264 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
265 CSPR_PORT_SIZE_16 | \
268 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
269 /* NOR Flash Timing Params */
270 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
271 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
272 FTIM0_NOR_TEADC(0x5) | \
273 FTIM0_NOR_TEAHC(0x5))
274 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
275 FTIM1_NOR_TRAD_NOR(0x1A) |\
276 FTIM1_NOR_TSEQRAD_NOR(0x13))
277 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
278 FTIM2_NOR_TCH(0x4) | \
279 FTIM2_NOR_TWPH(0x0E) | \
281 #define CONFIG_SYS_NOR_FTIM3 0x0
283 #define CONFIG_SYS_FLASH_QUIET_TEST
284 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
286 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
287 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
288 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
289 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
291 #define CONFIG_SYS_FLASH_EMPTY_INFO
292 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
293 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
294 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
295 #define QIXIS_BASE 0xffdf0000
296 #ifdef CONFIG_PHYS_64BIT
297 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
299 #define QIXIS_BASE_PHYS QIXIS_BASE
301 #define QIXIS_LBMAP_SWITCH 0x06
302 #define QIXIS_LBMAP_MASK 0x0f
303 #define QIXIS_LBMAP_SHIFT 0
304 #define QIXIS_LBMAP_DFLTBANK 0x00
305 #define QIXIS_LBMAP_ALTBANK 0x04
306 #define QIXIS_RST_CTL_RESET 0x31
307 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
308 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
309 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
310 #define QIXIS_RST_FORCE_MEM 0x01
312 #define CONFIG_SYS_CSPR3_EXT (0xf)
313 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
317 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
318 #define CONFIG_SYS_CSOR3 0x0
319 /* QIXIS Timing parameters for IFC CS3 */
320 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
321 FTIM0_GPCM_TEADC(0x0e) | \
322 FTIM0_GPCM_TEAHC(0x0e))
323 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
324 FTIM1_GPCM_TRAD(0x3f))
325 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
326 FTIM2_GPCM_TCH(0x8) | \
327 FTIM2_GPCM_TWP(0x1f))
328 #define CONFIG_SYS_CS3_FTIM3 0x0
330 #define CONFIG_NAND_FSL_IFC
331 #define CONFIG_SYS_NAND_BASE 0xff800000
332 #ifdef CONFIG_PHYS_64BIT
333 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
335 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
337 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
338 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
339 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
340 | CSPR_MSEL_NAND /* MSEL = NAND */ \
342 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
344 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
345 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
346 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
347 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
348 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
349 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
350 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
352 #define CONFIG_SYS_NAND_ONFI_DETECTION
354 /* ONFI NAND Flash mode0 Timing Params */
355 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
356 FTIM0_NAND_TWP(0x18) | \
357 FTIM0_NAND_TWCHT(0x07) | \
358 FTIM0_NAND_TWH(0x0a))
359 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
360 FTIM1_NAND_TWBE(0x39) | \
361 FTIM1_NAND_TRR(0x0e) | \
362 FTIM1_NAND_TRP(0x18))
363 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
364 FTIM2_NAND_TREH(0x0a) | \
365 FTIM2_NAND_TWHRE(0x1e))
366 #define CONFIG_SYS_NAND_FTIM3 0x0
368 #define CONFIG_SYS_NAND_DDR_LAW 11
369 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
370 #define CONFIG_SYS_MAX_NAND_DEVICE 1
371 #define CONFIG_CMD_NAND
373 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
375 #if defined(CONFIG_NAND)
376 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
377 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
378 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
379 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
380 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
381 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
382 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
383 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
384 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
385 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
386 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
387 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
388 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
389 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
390 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
391 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
392 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
393 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
394 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
395 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
396 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
397 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
398 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
399 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
401 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
402 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
403 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
404 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
405 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
406 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
407 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
408 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
409 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
410 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
411 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
412 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
413 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
414 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
415 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
416 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
417 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
418 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
419 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
420 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
421 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
422 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
423 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
424 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
427 #ifdef CONFIG_SPL_BUILD
428 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
430 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
433 #if defined(CONFIG_RAMBOOT_PBL)
434 #define CONFIG_SYS_RAMBOOT
437 #define CONFIG_BOARD_EARLY_INIT_R
438 #define CONFIG_MISC_INIT_R
440 #define CONFIG_HWCONFIG
442 /* define to use L1 as initial stack */
443 #define CONFIG_L1_INIT_RAM
444 #define CONFIG_SYS_INIT_RAM_LOCK
445 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
446 #ifdef CONFIG_PHYS_64BIT
447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
449 /* The assembler doesn't like typecast */
450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
451 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
452 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
458 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
460 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
461 GENERATED_GBL_DATA_SIZE)
462 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
464 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
465 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
468 #define CONFIG_CONS_INDEX 1
469 #define CONFIG_SYS_NS16550_SERIAL
470 #define CONFIG_SYS_NS16550_REG_SIZE 1
471 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
473 #define CONFIG_SYS_BAUDRATE_TABLE \
474 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
476 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
477 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
478 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
479 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
482 #ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */
483 #define CONFIG_FSL_DIU_FB
484 #ifdef CONFIG_FSL_DIU_FB
485 #define CONFIG_FSL_DIU_CH7301
486 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
487 #define CONFIG_VIDEO_LOGO
488 #define CONFIG_VIDEO_BMP_LOGO
489 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
491 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
492 * disable empty flash sector detection, which is I/O-intensive.
494 #undef CONFIG_SYS_FLASH_EMPTY_INFO
499 #define CONFIG_SYS_I2C
500 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
501 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
502 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
503 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
504 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
505 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
506 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
508 #define I2C_MUX_PCA_ADDR 0x77
509 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
510 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
511 #define I2C_RETIMER_ADDR 0x18
513 /* I2C bus multiplexer */
514 #define I2C_MUX_CH_DEFAULT 0x8
515 #define I2C_MUX_CH_DIU 0xC
516 #define I2C_MUX_CH5 0xD
517 #define I2C_MUX_CH7 0xF
519 /* LDI/DVI Encoder for display */
520 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
521 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
527 #define CONFIG_RTC_DS3231 1
528 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
531 * eSPI - Enhanced SPI
533 #ifndef CONFIG_SPL_BUILD
535 #define CONFIG_SPI_FLASH_BAR
536 #define CONFIG_SF_DEFAULT_SPEED 10000000
537 #define CONFIG_SF_DEFAULT_MODE 0
541 * Memory space is mapped 1-1, but I/O space must start from 0.
543 #define CONFIG_PCIE1 /* PCIE controller 1 */
544 #define CONFIG_PCIE2 /* PCIE controller 2 */
545 #define CONFIG_PCIE3 /* PCIE controller 3 */
546 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
547 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
548 #define CONFIG_PCI_INDIRECT_BRIDGE
551 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
553 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
554 #ifdef CONFIG_PHYS_64BIT
555 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
556 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
558 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
559 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
561 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
562 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
563 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
564 #ifdef CONFIG_PHYS_64BIT
565 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
567 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
569 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
572 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
574 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
575 #ifdef CONFIG_PHYS_64BIT
576 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
577 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
579 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
580 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
582 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
583 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
584 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
585 #ifdef CONFIG_PHYS_64BIT
586 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
588 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
590 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
593 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
595 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
596 #ifdef CONFIG_PHYS_64BIT
597 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
598 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
600 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
601 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
603 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
604 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
605 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
606 #ifdef CONFIG_PHYS_64BIT
607 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
609 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
611 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
614 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
615 #endif /* CONFIG_PCI */
620 #define CONFIG_FSL_SATA_V2
621 #ifdef CONFIG_FSL_SATA_V2
622 #define CONFIG_LIBATA
623 #define CONFIG_FSL_SATA
624 #define CONFIG_SYS_SATA_MAX_DEVICE 1
626 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
627 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
634 #define CONFIG_HAS_FSL_DR_USB
636 #ifdef CONFIG_HAS_FSL_DR_USB
637 #define CONFIG_USB_EHCI_FSL
638 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
645 #define CONFIG_FSL_ESDHC
646 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
650 #ifndef CONFIG_NOBQFMAN
651 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
652 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
653 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
654 #ifdef CONFIG_PHYS_64BIT
655 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
657 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
659 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
660 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
661 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
662 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
663 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
664 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
665 CONFIG_SYS_BMAN_CENA_SIZE)
666 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
667 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
668 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
669 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
670 #ifdef CONFIG_PHYS_64BIT
671 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
673 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
675 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
676 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
677 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
678 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
679 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
680 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
681 CONFIG_SYS_QMAN_CENA_SIZE)
682 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
683 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
685 #define CONFIG_SYS_DPAA_FMAN
689 /* Default address of microcode for the Linux FMan driver */
690 #if defined(CONFIG_SPIFLASH)
692 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
693 * env, so we got 0x110000.
695 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
696 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
697 #define CONFIG_SYS_QE_FW_ADDR 0x130000
698 #elif defined(CONFIG_SDCARD)
700 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
701 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
702 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
704 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
705 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
706 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
707 #elif defined(CONFIG_NAND)
708 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
709 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
710 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
711 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
713 * Slave has no ucode locally, it can fetch this from remote. When implementing
714 * in two corenet boards, slave's ucode could be stored in master's memory
715 * space, the address can be mapped from slave TLB->slave LAW->
716 * slave SRIO or PCIE outbound window->master inbound window->
717 * master LAW->the ucode address in master's memory space.
719 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
720 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
722 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
723 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
724 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
726 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
727 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
728 #endif /* CONFIG_NOBQFMAN */
730 #ifdef CONFIG_SYS_DPAA_FMAN
731 #define CONFIG_FMAN_ENET
732 #define CONFIG_PHYLIB_10G
733 #define CONFIG_PHY_VITESSE
734 #define CONFIG_PHY_REALTEK
735 #define CONFIG_PHY_TERANETICS
736 #define RGMII_PHY1_ADDR 0x1
737 #define RGMII_PHY2_ADDR 0x2
738 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
739 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
740 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
741 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
742 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
743 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
744 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
747 #ifdef CONFIG_FMAN_ENET
748 #define CONFIG_MII /* MII PHY management */
749 #define CONFIG_ETHPRIME "FM1@DTSEC4"
750 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
754 * Dynamic MTD Partition support with mtdparts
756 #ifdef CONFIG_MTD_NOR_FLASH
757 #define CONFIG_MTD_DEVICE
758 #define CONFIG_MTD_PARTITIONS
759 #define CONFIG_FLASH_CFI_MTD
760 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
762 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
763 "128k(dtb),96m(fs),-(user);"\
764 "fff800000.flash:2m(uboot),9m(kernel),"\
765 "128k(dtb),96m(fs),-(user);spife110000.0:" \
766 "2m(uboot),9m(kernel),128k(dtb),-(user)"
772 #define CONFIG_LOADS_ECHO /* echo on for serial download */
773 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
776 * Command line configuration.
778 #define CONFIG_CMD_REGINFO
781 #define CONFIG_CMD_PCI
785 * Miscellaneous configurable options
787 #define CONFIG_SYS_LONGHELP /* undef to save memory */
788 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
789 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
790 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
791 #ifdef CONFIG_CMD_KGDB
792 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
794 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
796 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
797 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
798 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
801 * For booting Linux, the board info and command line data
802 * have to be in the first 64 MB of memory, since this is
803 * the maximum mapped by the Linux kernel during initialization.
805 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
806 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
808 #ifdef CONFIG_CMD_KGDB
809 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
813 * Environment Configuration
815 #define CONFIG_ROOTPATH "/opt/nfsroot"
816 #define CONFIG_BOOTFILE "uImage"
817 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
818 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
819 #define __USB_PHY_TYPE utmi
821 #define CONFIG_EXTRA_ENV_SETTINGS \
822 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
823 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
824 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
825 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
826 "fdtfile=t1024qds/t1024qds.dtb\0" \
828 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
829 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
830 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
831 "tftpflash=tftpboot $loadaddr $uboot && " \
832 "protect off $ubootaddr +$filesize && " \
833 "erase $ubootaddr +$filesize && " \
834 "cp.b $loadaddr $ubootaddr $filesize && " \
835 "protect on $ubootaddr +$filesize && " \
836 "cmp.b $loadaddr $ubootaddr $filesize\0" \
837 "consoledev=ttyS0\0" \
838 "ramdiskaddr=2000000\0" \
842 #define CONFIG_LINUX \
843 "setenv bootargs root=/dev/ram rw " \
844 "console=$consoledev,$baudrate $othbootargs;" \
845 "setenv ramdiskaddr 0x02000000;" \
846 "setenv fdtaddr 0x00c00000;" \
847 "setenv loadaddr 0x1000000;" \
848 "bootm $loadaddr $ramdiskaddr $fdtaddr"
850 #define CONFIG_NFSBOOTCOMMAND \
851 "setenv bootargs root=/dev/nfs rw " \
852 "nfsroot=$serverip:$rootpath " \
853 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
854 "console=$consoledev,$baudrate $othbootargs;" \
855 "tftp $loadaddr $bootfile;" \
856 "tftp $fdtaddr $fdtfile;" \
857 "bootm $loadaddr - $fdtaddr"
859 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
861 #include <asm/fsl_secure_boot.h>
863 #endif /* __T1024QDS_H */