2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T1024/T1023 RDB board configuration file
14 /* High Level Configuration Options */
15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
16 #define CONFIG_MP /* support multiple processors */
17 #define CONFIG_ENABLE_36BIT_PHYS
19 #ifdef CONFIG_PHYS_64BIT
20 #define CONFIG_ADDR_MAP 1
21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
27 #define CONFIG_ENV_OVERWRITE
29 /* support deep sleep */
30 #ifdef CONFIG_ARCH_T1024
31 #define CONFIG_DEEP_SLEEP
34 #ifdef CONFIG_RAMBOOT_PBL
35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
36 #define CONFIG_SPL_FLUSH_IMAGE
37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
38 #define CONFIG_SYS_TEXT_BASE 0x30001000
39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
40 #define CONFIG_SPL_PAD_TO 0x40000
41 #define CONFIG_SPL_MAX_SIZE 0x28000
42 #define RESET_VECTOR_OFFSET 0x27FFC
43 #define BOOT_PAGE_OFFSET 0x27000
44 #ifdef CONFIG_SPL_BUILD
45 #define CONFIG_SPL_SKIP_RELOCATE
46 #define CONFIG_SPL_COMMON_INIT_DDR
47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
53 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
54 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
56 #if defined(CONFIG_TARGET_T1024RDB)
57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
58 #elif defined(CONFIG_TARGET_T1023RDB)
59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
61 #define CONFIG_SPL_NAND_BOOT
64 #ifdef CONFIG_SPIFLASH
65 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
66 #define CONFIG_SPL_SPI_FLASH_MINIMAL
67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
71 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
72 #ifndef CONFIG_SPL_BUILD
73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
75 #if defined(CONFIG_TARGET_T1024RDB)
76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
77 #elif defined(CONFIG_TARGET_T1023RDB)
78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
80 #define CONFIG_SPL_SPI_BOOT
84 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
85 #define CONFIG_SPL_MMC_MINIMAL
86 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
87 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
88 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
89 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
91 #ifndef CONFIG_SPL_BUILD
92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
94 #if defined(CONFIG_TARGET_T1024RDB)
95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
96 #elif defined(CONFIG_TARGET_T1023RDB)
97 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
99 #define CONFIG_SPL_MMC_BOOT
102 #endif /* CONFIG_RAMBOOT_PBL */
104 #ifndef CONFIG_SYS_TEXT_BASE
105 #define CONFIG_SYS_TEXT_BASE 0xeff40000
108 #ifndef CONFIG_RESET_VECTOR_ADDRESS
109 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
112 #ifdef CONFIG_MTD_NOR_FLASH
113 #define CONFIG_FLASH_CFI_DRIVER
114 #define CONFIG_SYS_FLASH_CFI
115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
118 /* PCIe Boot - Master */
119 #define CONFIG_SRIO_PCIE_BOOT_MASTER
121 * for slave u-boot IMAGE instored in master memory space,
122 * PHYS must be aligned based on the SIZE
124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
126 #ifdef CONFIG_PHYS_64BIT
127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
134 * for slave UCODE and ENV instored in master memory space,
135 * PHYS must be aligned based on the SIZE
137 #ifdef CONFIG_PHYS_64BIT
138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
145 /* slave core release by master*/
146 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
147 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
149 /* PCIe Boot - Slave */
150 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
151 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
152 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
153 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
154 /* Set 1M boot space for PCIe boot */
155 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
156 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
157 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
158 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
161 #if defined(CONFIG_SPIFLASH)
162 #define CONFIG_SYS_EXTRA_ENV_RELOC
163 #define CONFIG_ENV_SPI_BUS 0
164 #define CONFIG_ENV_SPI_CS 0
165 #define CONFIG_ENV_SPI_MAX_HZ 10000000
166 #define CONFIG_ENV_SPI_MODE 0
167 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
168 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
169 #if defined(CONFIG_TARGET_T1024RDB)
170 #define CONFIG_ENV_SECT_SIZE 0x10000
171 #elif defined(CONFIG_TARGET_T1023RDB)
172 #define CONFIG_ENV_SECT_SIZE 0x40000
174 #elif defined(CONFIG_SDCARD)
175 #define CONFIG_SYS_EXTRA_ENV_RELOC
176 #define CONFIG_SYS_MMC_ENV_DEV 0
177 #define CONFIG_ENV_SIZE 0x2000
178 #define CONFIG_ENV_OFFSET (512 * 0x800)
179 #elif defined(CONFIG_NAND)
180 #define CONFIG_SYS_EXTRA_ENV_RELOC
181 #define CONFIG_ENV_SIZE 0x2000
182 #if defined(CONFIG_TARGET_T1024RDB)
183 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
184 #elif defined(CONFIG_TARGET_T1023RDB)
185 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
187 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
188 #define CONFIG_ENV_IS_IN_REMOTE
189 #define CONFIG_ENV_ADDR 0xffe20000
190 #define CONFIG_ENV_SIZE 0x2000
191 #elif defined(CONFIG_ENV_IS_NOWHERE)
192 #define CONFIG_ENV_SIZE 0x2000
194 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
195 #define CONFIG_ENV_SIZE 0x2000
196 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
200 unsigned long get_board_sys_clk(void);
201 unsigned long get_board_ddr_clk(void);
204 #define CONFIG_SYS_CLK_FREQ 100000000
205 #define CONFIG_DDR_CLK_FREQ 100000000
208 * These can be toggled for performance analysis, otherwise use default.
210 #define CONFIG_SYS_CACHE_STASHING
211 #define CONFIG_BACKSIDE_L2_CACHE
212 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
213 #define CONFIG_BTB /* toggle branch predition */
214 #define CONFIG_DDR_ECC
215 #ifdef CONFIG_DDR_ECC
216 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
217 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
220 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
221 #define CONFIG_SYS_MEMTEST_END 0x00400000
222 #define CONFIG_SYS_ALT_MEMTEST
223 #define CONFIG_PANIC_HANG /* do not reset board on panic */
226 * Config the L3 Cache as L3 SRAM
228 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
229 #define CONFIG_SYS_L3_SIZE (256 << 10)
230 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
231 #ifdef CONFIG_RAMBOOT_PBL
232 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
234 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
235 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
236 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
237 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
239 #ifdef CONFIG_PHYS_64BIT
240 #define CONFIG_SYS_DCSRBAR 0xf0000000
241 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
245 #define CONFIG_ID_EEPROM
246 #define CONFIG_SYS_I2C_EEPROM_NXID
247 #define CONFIG_SYS_EEPROM_BUS_NUM 0
248 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
249 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
250 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
251 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
256 #define CONFIG_VERY_BIG_RAM
257 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
258 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
259 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
260 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
261 #define CONFIG_FSL_DDR_INTERACTIVE
262 #if defined(CONFIG_TARGET_T1024RDB)
263 #define CONFIG_DDR_SPD
264 #define CONFIG_SYS_SPD_BUS_NUM 0
265 #define SPD_EEPROM_ADDRESS 0x51
266 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
267 #elif defined(CONFIG_TARGET_T1023RDB)
268 #define CONFIG_SYS_DDR_RAW_TIMING
269 #define CONFIG_SYS_SDRAM_SIZE 2048
275 #define CONFIG_SYS_FLASH_BASE 0xe8000000
276 #ifdef CONFIG_PHYS_64BIT
277 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
279 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
282 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
283 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
284 CSPR_PORT_SIZE_16 | \
287 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
289 /* NOR Flash Timing Params */
290 #if defined(CONFIG_TARGET_T1024RDB)
291 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
292 #elif defined(CONFIG_TARGET_T1023RDB)
293 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
294 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
296 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
297 FTIM0_NOR_TEADC(0x5) | \
298 FTIM0_NOR_TEAHC(0x5))
299 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
300 FTIM1_NOR_TRAD_NOR(0x1A) |\
301 FTIM1_NOR_TSEQRAD_NOR(0x13))
302 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
303 FTIM2_NOR_TCH(0x4) | \
304 FTIM2_NOR_TWPH(0x0E) | \
306 #define CONFIG_SYS_NOR_FTIM3 0x0
308 #define CONFIG_SYS_FLASH_QUIET_TEST
309 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
311 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
312 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
313 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
314 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
316 #define CONFIG_SYS_FLASH_EMPTY_INFO
317 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
319 #ifdef CONFIG_TARGET_T1024RDB
321 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
322 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
323 #define CONFIG_SYS_CSPR2_EXT (0xf)
324 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
328 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
329 #define CONFIG_SYS_CSOR2 0x0
331 /* CPLD Timing parameters for IFC CS2 */
332 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
333 FTIM0_GPCM_TEADC(0x0e) | \
334 FTIM0_GPCM_TEAHC(0x0e))
335 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
336 FTIM1_GPCM_TRAD(0x1f))
337 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
338 FTIM2_GPCM_TCH(0x8) | \
339 FTIM2_GPCM_TWP(0x1f))
340 #define CONFIG_SYS_CS2_FTIM3 0x0
343 /* NAND Flash on IFC */
344 #define CONFIG_NAND_FSL_IFC
345 #define CONFIG_SYS_NAND_BASE 0xff800000
346 #ifdef CONFIG_PHYS_64BIT
347 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
349 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
351 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
352 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
353 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
354 | CSPR_MSEL_NAND /* MSEL = NAND */ \
356 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
358 #if defined(CONFIG_TARGET_T1024RDB)
359 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
360 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
361 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
362 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
363 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
364 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
365 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
366 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
367 #elif defined(CONFIG_TARGET_T1023RDB)
368 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
369 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
370 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
371 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
372 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
373 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
374 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
375 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
378 #define CONFIG_SYS_NAND_ONFI_DETECTION
379 /* ONFI NAND Flash mode0 Timing Params */
380 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
381 FTIM0_NAND_TWP(0x18) | \
382 FTIM0_NAND_TWCHT(0x07) | \
383 FTIM0_NAND_TWH(0x0a))
384 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
385 FTIM1_NAND_TWBE(0x39) | \
386 FTIM1_NAND_TRR(0x0e) | \
387 FTIM1_NAND_TRP(0x18))
388 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
389 FTIM2_NAND_TREH(0x0a) | \
390 FTIM2_NAND_TWHRE(0x1e))
391 #define CONFIG_SYS_NAND_FTIM3 0x0
393 #define CONFIG_SYS_NAND_DDR_LAW 11
394 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
395 #define CONFIG_SYS_MAX_NAND_DEVICE 1
396 #define CONFIG_CMD_NAND
398 #if defined(CONFIG_NAND)
399 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
400 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
401 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
402 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
403 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
404 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
405 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
406 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
407 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
408 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
409 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
410 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
411 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
412 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
413 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
414 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
416 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
417 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
418 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
419 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
420 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
421 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
422 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
423 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
424 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
425 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
426 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
427 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
428 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
429 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
430 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
431 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
434 #ifdef CONFIG_SPL_BUILD
435 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
437 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
440 #if defined(CONFIG_RAMBOOT_PBL)
441 #define CONFIG_SYS_RAMBOOT
444 #define CONFIG_BOARD_EARLY_INIT_R
445 #define CONFIG_MISC_INIT_R
447 #define CONFIG_HWCONFIG
449 /* define to use L1 as initial stack */
450 #define CONFIG_L1_INIT_RAM
451 #define CONFIG_SYS_INIT_RAM_LOCK
452 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
453 #ifdef CONFIG_PHYS_64BIT
454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
456 /* The assembler doesn't like typecast */
457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
458 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
459 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
465 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
467 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
468 GENERATED_GBL_DATA_SIZE)
469 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
471 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
472 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
475 #define CONFIG_CONS_INDEX 1
476 #define CONFIG_SYS_NS16550_SERIAL
477 #define CONFIG_SYS_NS16550_REG_SIZE 1
478 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
480 #define CONFIG_SYS_BAUDRATE_TABLE \
481 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
483 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
484 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
485 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
486 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
489 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
490 #ifdef CONFIG_FSL_DIU_FB
491 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
492 #define CONFIG_VIDEO_LOGO
493 #define CONFIG_VIDEO_BMP_LOGO
494 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
496 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
497 * disable empty flash sector detection, which is I/O-intensive.
499 #undef CONFIG_SYS_FLASH_EMPTY_INFO
503 #define CONFIG_SYS_I2C
504 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
505 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
506 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
507 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
508 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
509 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
510 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
512 #define I2C_PCA6408_BUS_NUM 1
513 #define I2C_PCA6408_ADDR 0x20
515 /* I2C bus multiplexer */
516 #define I2C_MUX_CH_DEFAULT 0x8
522 #define CONFIG_RTC_DS1337 1
523 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
526 * eSPI - Enhanced SPI
528 #define CONFIG_SPI_FLASH_BAR
529 #define CONFIG_SF_DEFAULT_SPEED 10000000
530 #define CONFIG_SF_DEFAULT_MODE 0
534 * Memory space is mapped 1-1, but I/O space must start from 0.
536 #define CONFIG_PCIE1 /* PCIE controller 1 */
537 #define CONFIG_PCIE2 /* PCIE controller 2 */
538 #define CONFIG_PCIE3 /* PCIE controller 3 */
539 #ifdef CONFIG_ARCH_T1040
540 #define CONFIG_PCIE4 /* PCIE controller 4 */
542 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
543 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
544 #define CONFIG_PCI_INDIRECT_BRIDGE
547 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
549 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
550 #ifdef CONFIG_PHYS_64BIT
551 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
552 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
554 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
555 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
557 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
558 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
559 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
560 #ifdef CONFIG_PHYS_64BIT
561 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
563 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
565 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
568 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
570 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
571 #ifdef CONFIG_PHYS_64BIT
572 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
573 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
575 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
576 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
578 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
579 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
580 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
581 #ifdef CONFIG_PHYS_64BIT
582 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
584 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
586 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
589 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
591 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
592 #ifdef CONFIG_PHYS_64BIT
593 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
594 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
596 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
597 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
599 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
600 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
601 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
602 #ifdef CONFIG_PHYS_64BIT
603 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
605 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
607 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
610 /* controller 4, Base address 203000, to be removed */
612 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
613 #ifdef CONFIG_PHYS_64BIT
614 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
615 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
617 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
618 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
620 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
621 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
622 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
623 #ifdef CONFIG_PHYS_64BIT
624 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
626 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
628 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
631 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
632 #endif /* CONFIG_PCI */
637 #define CONFIG_HAS_FSL_DR_USB
639 #ifdef CONFIG_HAS_FSL_DR_USB
640 #define CONFIG_USB_EHCI_FSL
641 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
648 #define CONFIG_FSL_ESDHC
649 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
653 #ifndef CONFIG_NOBQFMAN
654 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
655 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
656 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
657 #ifdef CONFIG_PHYS_64BIT
658 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
660 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
662 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
663 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
664 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
665 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
666 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
667 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
668 CONFIG_SYS_BMAN_CENA_SIZE)
669 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
670 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
671 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
672 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
673 #ifdef CONFIG_PHYS_64BIT
674 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
676 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
678 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
679 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
680 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
681 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
682 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
683 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
684 CONFIG_SYS_QMAN_CENA_SIZE)
685 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
686 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
688 #define CONFIG_SYS_DPAA_FMAN
690 #ifdef CONFIG_TARGET_T1024RDB
694 /* Default address of microcode for the Linux FMan driver */
695 #if defined(CONFIG_SPIFLASH)
697 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
698 * env, so we got 0x110000.
700 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
701 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
702 #define CONFIG_SYS_QE_FW_ADDR 0x130000
703 #elif defined(CONFIG_SDCARD)
705 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
706 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
707 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
709 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
710 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
711 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
712 #elif defined(CONFIG_NAND)
713 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
714 #if defined(CONFIG_TARGET_T1024RDB)
715 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
716 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
717 #elif defined(CONFIG_TARGET_T1023RDB)
718 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
719 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
721 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
723 * Slave has no ucode locally, it can fetch this from remote. When implementing
724 * in two corenet boards, slave's ucode could be stored in master's memory
725 * space, the address can be mapped from slave TLB->slave LAW->
726 * slave SRIO or PCIE outbound window->master inbound window->
727 * master LAW->the ucode address in master's memory space.
729 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
730 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
732 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
733 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
734 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
736 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
737 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
738 #endif /* CONFIG_NOBQFMAN */
740 #ifdef CONFIG_SYS_DPAA_FMAN
741 #define CONFIG_FMAN_ENET
742 #define CONFIG_PHYLIB_10G
743 #define CONFIG_PHY_REALTEK
744 #define CONFIG_PHY_AQUANTIA
745 #if defined(CONFIG_TARGET_T1024RDB)
746 #define RGMII_PHY1_ADDR 0x2
747 #define RGMII_PHY2_ADDR 0x6
748 #define SGMII_AQR_PHY_ADDR 0x2
749 #define FM1_10GEC1_PHY_ADDR 0x1
750 #elif defined(CONFIG_TARGET_T1023RDB)
751 #define RGMII_PHY1_ADDR 0x1
752 #define SGMII_RTK_PHY_ADDR 0x3
753 #define SGMII_AQR_PHY_ADDR 0x2
757 #ifdef CONFIG_FMAN_ENET
758 #define CONFIG_MII /* MII PHY management */
759 #define CONFIG_ETHPRIME "FM1@DTSEC4"
760 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
764 * Dynamic MTD Partition support with mtdparts
766 #ifdef CONFIG_MTD_NOR_FLASH
767 #define CONFIG_MTD_DEVICE
768 #define CONFIG_MTD_PARTITIONS
769 #define CONFIG_FLASH_CFI_MTD
770 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
772 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
773 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
774 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
775 "1m(uboot),5m(kernel),128k(dtb),-(user)"
781 #define CONFIG_LOADS_ECHO /* echo on for serial download */
782 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
785 * Command line configuration.
787 #define CONFIG_CMD_REGINFO
790 #define CONFIG_CMD_PCI
794 * Miscellaneous configurable options
796 #define CONFIG_SYS_LONGHELP /* undef to save memory */
797 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
798 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
799 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
800 #ifdef CONFIG_CMD_KGDB
801 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
803 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
805 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
806 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
807 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
810 * For booting Linux, the board info and command line data
811 * have to be in the first 64 MB of memory, since this is
812 * the maximum mapped by the Linux kernel during initialization.
814 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
815 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
817 #ifdef CONFIG_CMD_KGDB
818 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
822 * Environment Configuration
824 #define CONFIG_ROOTPATH "/opt/nfsroot"
825 #define CONFIG_BOOTFILE "uImage"
826 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
827 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
828 #define __USB_PHY_TYPE utmi
830 #ifdef CONFIG_ARCH_T1024
831 #define CONFIG_BOARDNAME t1024rdb
832 #define BANK_INTLV cs0_cs1
834 #define CONFIG_BOARDNAME t1023rdb
835 #define BANK_INTLV null
838 #define CONFIG_EXTRA_ENV_SETTINGS \
839 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
840 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
841 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
842 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
843 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
844 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
845 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
846 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
847 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
849 "tftpflash=tftpboot $loadaddr $uboot && " \
850 "protect off $ubootaddr +$filesize && " \
851 "erase $ubootaddr +$filesize && " \
852 "cp.b $loadaddr $ubootaddr $filesize && " \
853 "protect on $ubootaddr +$filesize && " \
854 "cmp.b $loadaddr $ubootaddr $filesize\0" \
855 "consoledev=ttyS0\0" \
856 "ramdiskaddr=2000000\0" \
857 "fdtaddr=1e00000\0" \
860 #define CONFIG_LINUX \
861 "setenv bootargs root=/dev/ram rw " \
862 "console=$consoledev,$baudrate $othbootargs;" \
863 "setenv ramdiskaddr 0x02000000;" \
864 "setenv fdtaddr 0x00c00000;" \
865 "setenv loadaddr 0x1000000;" \
866 "bootm $loadaddr $ramdiskaddr $fdtaddr"
868 #define CONFIG_NFSBOOTCOMMAND \
869 "setenv bootargs root=/dev/nfs rw " \
870 "nfsroot=$serverip:$rootpath " \
871 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
872 "console=$consoledev,$baudrate $othbootargs;" \
873 "tftp $loadaddr $bootfile;" \
874 "tftp $fdtaddr $fdtfile;" \
875 "bootm $loadaddr - $fdtaddr"
877 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
879 #include <asm/fsl_secure_boot.h>
881 #endif /* __T1024RDB_H */