2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * T1040 QDS board configuration file
29 #define CONFIG_T1040QDS
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
38 /* High Level Configuration Options */
40 #define CONFIG_E500 /* BOOKE e500 family */
41 #define CONFIG_E500MC /* BOOKE e500mc family */
42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
43 #define CONFIG_MP /* support multiple processors */
45 /* support deep sleep */
46 #define CONFIG_DEEP_SLEEP
47 #if defined(CONFIG_DEEP_SLEEP)
48 #define CONFIG_BOARD_EARLY_INIT_F
51 #ifndef CONFIG_SYS_TEXT_BASE
52 #define CONFIG_SYS_TEXT_BASE 0xeff40000
55 #ifndef CONFIG_RESET_VECTOR_ADDRESS
56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
60 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
61 #define CONFIG_FSL_IFC /* Enable IFC Support */
62 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
63 #define CONFIG_PCI /* Enable PCI/PCIE */
64 #define CONFIG_PCI_INDIRECT_BRIDGE
65 #define CONFIG_PCIE1 /* PCIE controller 1 */
66 #define CONFIG_PCIE2 /* PCIE controller 2 */
67 #define CONFIG_PCIE3 /* PCIE controller 3 */
68 #define CONFIG_PCIE4 /* PCIE controller 4 */
70 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
71 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
73 #define CONFIG_FSL_LAW /* Use common FSL init code */
75 #define CONFIG_ENV_OVERWRITE
77 #ifdef CONFIG_SYS_NO_FLASH
78 #define CONFIG_ENV_IS_NOWHERE
80 #define CONFIG_FLASH_CFI_DRIVER
81 #define CONFIG_SYS_FLASH_CFI
82 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
85 #ifndef CONFIG_SYS_NO_FLASH
86 #if defined(CONFIG_SPIFLASH)
87 #define CONFIG_SYS_EXTRA_ENV_RELOC
88 #define CONFIG_ENV_IS_IN_SPI_FLASH
89 #define CONFIG_ENV_SPI_BUS 0
90 #define CONFIG_ENV_SPI_CS 0
91 #define CONFIG_ENV_SPI_MAX_HZ 10000000
92 #define CONFIG_ENV_SPI_MODE 0
93 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
94 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
95 #define CONFIG_ENV_SECT_SIZE 0x10000
96 #elif defined(CONFIG_SDCARD)
97 #define CONFIG_SYS_EXTRA_ENV_RELOC
98 #define CONFIG_ENV_IS_IN_MMC
99 #define CONFIG_SYS_MMC_ENV_DEV 0
100 #define CONFIG_ENV_SIZE 0x2000
101 #define CONFIG_ENV_OFFSET (512 * 1658)
102 #elif defined(CONFIG_NAND)
103 #define CONFIG_SYS_EXTRA_ENV_RELOC
104 #define CONFIG_ENV_IS_IN_NAND
105 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
106 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
108 #define CONFIG_ENV_IS_IN_FLASH
109 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
110 #define CONFIG_ENV_SIZE 0x2000
111 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
113 #else /* CONFIG_SYS_NO_FLASH */
114 #define CONFIG_ENV_SIZE 0x2000
115 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
119 unsigned long get_board_sys_clk(void);
120 unsigned long get_board_ddr_clk(void);
123 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
124 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
127 * These can be toggled for performance analysis, otherwise use default.
129 #define CONFIG_SYS_CACHE_STASHING
130 #define CONFIG_BACKSIDE_L2_CACHE
131 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
132 #define CONFIG_BTB /* toggle branch predition */
133 #define CONFIG_DDR_ECC
134 #ifdef CONFIG_DDR_ECC
135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
136 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
139 #define CONFIG_ENABLE_36BIT_PHYS
141 #define CONFIG_ADDR_MAP
142 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
144 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
145 #define CONFIG_SYS_MEMTEST_END 0x00400000
146 #define CONFIG_SYS_ALT_MEMTEST
147 #define CONFIG_PANIC_HANG /* do not reset board on panic */
150 * Config the L3 Cache as L3 SRAM
152 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
154 #define CONFIG_SYS_DCSRBAR 0xf0000000
155 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
158 #define CONFIG_ID_EEPROM
159 #define CONFIG_SYS_I2C_EEPROM_NXID
160 #define CONFIG_SYS_EEPROM_BUS_NUM 0
161 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
162 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
163 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
164 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
169 #define CONFIG_VERY_BIG_RAM
170 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
171 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
173 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
174 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
175 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
177 #define CONFIG_DDR_SPD
178 #ifndef CONFIG_SYS_FSL_DDR4
179 #define CONFIG_SYS_FSL_DDR3
181 #define CONFIG_FSL_DDR_INTERACTIVE
183 #define CONFIG_SYS_SPD_BUS_NUM 0
184 #define SPD_EEPROM_ADDRESS 0x51
186 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
191 #define CONFIG_SYS_FLASH_BASE 0xe0000000
192 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
194 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
195 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
197 CSPR_PORT_SIZE_16 | \
200 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
201 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
202 CSPR_PORT_SIZE_16 | \
205 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
210 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
212 /* NOR Flash Timing Params */
213 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
214 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
215 FTIM0_NOR_TEADC(0x5) | \
216 FTIM0_NOR_TEAHC(0x5))
217 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
218 FTIM1_NOR_TRAD_NOR(0x1A) |\
219 FTIM1_NOR_TSEQRAD_NOR(0x13))
220 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
221 FTIM2_NOR_TCH(0x4) | \
222 FTIM2_NOR_TWPH(0x0E) | \
224 #define CONFIG_SYS_NOR_FTIM3 0x0
226 #define CONFIG_SYS_FLASH_QUIET_TEST
227 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
229 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
230 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
231 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
234 #define CONFIG_SYS_FLASH_EMPTY_INFO
235 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
236 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
237 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
238 #define QIXIS_BASE 0xffdf0000
239 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
240 #define QIXIS_LBMAP_SWITCH 0x06
241 #define QIXIS_LBMAP_MASK 0x0f
242 #define QIXIS_LBMAP_SHIFT 0
243 #define QIXIS_LBMAP_DFLTBANK 0x00
244 #define QIXIS_LBMAP_ALTBANK 0x04
245 #define QIXIS_RST_CTL_RESET 0x31
246 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
247 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
248 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
249 #define QIXIS_RST_FORCE_MEM 0x01
251 #define CONFIG_SYS_CSPR3_EXT (0xf)
252 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
256 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
257 #define CONFIG_SYS_CSOR3 0x0
258 /* QIXIS Timing parameters for IFC CS3 */
259 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
260 FTIM0_GPCM_TEADC(0x0e) | \
261 FTIM0_GPCM_TEAHC(0x0e))
262 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
263 FTIM1_GPCM_TRAD(0x3f))
264 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
265 FTIM2_GPCM_TCH(0x8) | \
266 FTIM2_GPCM_TWP(0x1f))
267 #define CONFIG_SYS_CS3_FTIM3 0x0
269 #define CONFIG_NAND_FSL_IFC
270 #define CONFIG_SYS_NAND_BASE 0xff800000
271 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
273 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
274 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
275 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
276 | CSPR_MSEL_NAND /* MSEL = NAND */ \
278 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
280 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
281 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
282 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
283 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
284 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
285 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
286 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
288 #define CONFIG_SYS_NAND_ONFI_DETECTION
290 /* ONFI NAND Flash mode0 Timing Params */
291 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
292 FTIM0_NAND_TWP(0x18) | \
293 FTIM0_NAND_TWCHT(0x07) | \
294 FTIM0_NAND_TWH(0x0a))
295 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
296 FTIM1_NAND_TWBE(0x39) | \
297 FTIM1_NAND_TRR(0x0e) | \
298 FTIM1_NAND_TRP(0x18))
299 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
300 FTIM2_NAND_TREH(0x0a) | \
301 FTIM2_NAND_TWHRE(0x1e))
302 #define CONFIG_SYS_NAND_FTIM3 0x0
304 #define CONFIG_SYS_NAND_DDR_LAW 11
305 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
306 #define CONFIG_SYS_MAX_NAND_DEVICE 1
307 #define CONFIG_CMD_NAND
309 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
311 #if defined(CONFIG_NAND)
312 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
313 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
314 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
315 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
316 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
317 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
318 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
319 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
320 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
321 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
322 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
323 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
324 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
325 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
326 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
327 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
328 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
329 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
330 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
331 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
332 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
333 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
334 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
335 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
337 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
338 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
339 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
340 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
341 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
342 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
343 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
344 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
345 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
346 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
347 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
348 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
349 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
350 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
351 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
352 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
353 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
354 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
355 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
356 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
357 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
358 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
359 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
360 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
363 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
365 #if defined(CONFIG_RAMBOOT_PBL)
366 #define CONFIG_SYS_RAMBOOT
369 #define CONFIG_BOARD_EARLY_INIT_R
370 #define CONFIG_MISC_INIT_R
372 #define CONFIG_HWCONFIG
374 /* define to use L1 as initial stack */
375 #define CONFIG_L1_INIT_RAM
376 #define CONFIG_SYS_INIT_RAM_LOCK
377 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
380 /* The assembler doesn't like typecast */
381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
382 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
383 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
384 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
386 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
387 GENERATED_GBL_DATA_SIZE)
388 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
390 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
391 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
393 /* Serial Port - controlled on board with jumper J8
397 #define CONFIG_CONS_INDEX 1
398 #define CONFIG_SYS_NS16550_SERIAL
399 #define CONFIG_SYS_NS16550_REG_SIZE 1
400 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
402 #define CONFIG_SYS_BAUDRATE_TABLE \
403 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
405 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
406 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
407 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
408 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
409 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
412 #define CONFIG_FSL_DIU_FB
413 #ifdef CONFIG_FSL_DIU_FB
414 #define CONFIG_FSL_DIU_CH7301
415 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
417 #define CONFIG_CMD_BMP
418 #define CONFIG_CFB_CONSOLE
419 #define CONFIG_VIDEO_SW_CURSOR
420 #define CONFIG_VGA_AS_SINGLE_DEVICE
421 #define CONFIG_VIDEO_LOGO
422 #define CONFIG_VIDEO_BMP_LOGO
423 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
425 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
426 * disable empty flash sector detection, which is I/O-intensive.
428 #undef CONFIG_SYS_FLASH_EMPTY_INFO
432 #define CONFIG_SYS_I2C
433 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
434 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
435 #define CONFIG_SYS_FSL_I2C2_SPEED 50000
436 #define CONFIG_SYS_FSL_I2C3_SPEED 50000
437 #define CONFIG_SYS_FSL_I2C4_SPEED 50000
438 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
439 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
440 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
441 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
442 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
443 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
444 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
445 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
447 #define I2C_MUX_PCA_ADDR 0x77
448 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
450 /* I2C bus multiplexer */
451 #define I2C_MUX_CH_DEFAULT 0x8
452 #define I2C_MUX_CH_DIU 0xC
454 /* LDI/DVI Encoder for display */
455 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
456 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
462 #define CONFIG_RTC_DS3231 1
463 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
466 * eSPI - Enhanced SPI
468 #define CONFIG_SF_DEFAULT_SPEED 10000000
469 #define CONFIG_SF_DEFAULT_MODE 0
473 * Memory space is mapped 1-1, but I/O space must start from 0.
477 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
479 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
480 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
481 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
482 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
483 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
484 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
485 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
486 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
489 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
491 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
492 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
493 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
494 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
495 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
496 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
497 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
498 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
501 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
503 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
504 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
505 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
506 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
507 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
508 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
509 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
510 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
513 /* controller 4, Base address 203000 */
515 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
516 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
517 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
518 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
519 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
520 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
521 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
522 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
525 #define CONFIG_PCI_PNP /* do pci plug-and-play */
527 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
528 #define CONFIG_DOS_PARTITION
529 #endif /* CONFIG_PCI */
532 #define CONFIG_FSL_SATA_V2
533 #ifdef CONFIG_FSL_SATA_V2
534 #define CONFIG_LIBATA
535 #define CONFIG_FSL_SATA
537 #define CONFIG_SYS_SATA_MAX_DEVICE 2
539 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
540 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
542 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
543 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
546 #define CONFIG_CMD_SATA
547 #define CONFIG_DOS_PARTITION
553 #define CONFIG_HAS_FSL_DR_USB
555 #ifdef CONFIG_HAS_FSL_DR_USB
556 #define CONFIG_USB_EHCI
558 #ifdef CONFIG_USB_EHCI
559 #define CONFIG_USB_EHCI_FSL
560 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
567 #define CONFIG_FSL_ESDHC
568 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
569 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
570 #define CONFIG_GENERIC_MMC
571 #define CONFIG_DOS_PARTITION
572 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
576 #ifndef CONFIG_NOBQFMAN
577 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
578 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
579 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
580 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
581 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
582 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
583 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
584 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
585 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
586 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
587 CONFIG_SYS_BMAN_CENA_SIZE)
588 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
589 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
590 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
591 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
592 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
593 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
594 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
595 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
596 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
597 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
598 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
599 CONFIG_SYS_QMAN_CENA_SIZE)
600 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
601 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
603 #define CONFIG_SYS_DPAA_FMAN
604 #define CONFIG_SYS_DPAA_PME
608 /* Default address of microcode for the Linux Fman driver */
609 #if defined(CONFIG_SPIFLASH)
611 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
612 * env, so we got 0x110000.
614 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
615 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
616 #elif defined(CONFIG_SDCARD)
618 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
619 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
620 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
622 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
623 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
624 #elif defined(CONFIG_NAND)
625 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
626 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
628 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
629 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
630 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
632 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
633 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
634 #endif /* CONFIG_NOBQFMAN */
636 #ifdef CONFIG_SYS_DPAA_FMAN
637 #define CONFIG_FMAN_ENET
638 #define CONFIG_PHYLIB_10G
639 #define CONFIG_PHY_VITESSE
640 #define CONFIG_PHY_REALTEK
641 #define CONFIG_PHY_TERANETICS
642 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
643 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
644 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
645 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
648 #ifdef CONFIG_FMAN_ENET
649 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
650 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
652 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
653 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
654 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
655 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
657 #define CONFIG_MII /* MII PHY management */
658 #define CONFIG_ETHPRIME "FM1@DTSEC1"
659 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
662 /* Enable VSC9953 L2 Switch driver */
663 #define CONFIG_VSC9953
664 #define CONFIG_CMD_ETHSW
665 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
666 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
669 * Dynamic MTD Partition support with mtdparts
671 #ifndef CONFIG_SYS_NO_FLASH
672 #define CONFIG_MTD_DEVICE
673 #define CONFIG_MTD_PARTITIONS
674 #define CONFIG_CMD_MTDPARTS
675 #define CONFIG_FLASH_CFI_MTD
676 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
678 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
679 "128k(dtb),96m(fs),-(user);"\
680 "fff800000.flash:2m(uboot),9m(kernel),"\
681 "128k(dtb),96m(fs),-(user);spife110000.0:" \
682 "2m(uboot),9m(kernel),128k(dtb),-(user)"
688 #define CONFIG_LOADS_ECHO /* echo on for serial download */
689 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
692 * Command line configuration.
694 #define CONFIG_CMD_DATE
695 #define CONFIG_CMD_EEPROM
696 #define CONFIG_CMD_ERRATA
697 #define CONFIG_CMD_IRQ
698 #define CONFIG_CMD_REGINFO
701 #define CONFIG_CMD_PCI
704 /* Hash command with SHA acceleration supported in hardware */
705 #ifdef CONFIG_FSL_CAAM
706 #define CONFIG_CMD_HASH
707 #define CONFIG_SHA_HW_ACCEL
711 * Miscellaneous configurable options
713 #define CONFIG_SYS_LONGHELP /* undef to save memory */
714 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
715 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
716 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
717 #ifdef CONFIG_CMD_KGDB
718 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
720 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
722 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
723 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
724 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
727 * For booting Linux, the board info and command line data
728 * have to be in the first 64 MB of memory, since this is
729 * the maximum mapped by the Linux kernel during initialization.
731 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
732 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
734 #ifdef CONFIG_CMD_KGDB
735 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
739 * Environment Configuration
741 #define CONFIG_ROOTPATH "/opt/nfsroot"
742 #define CONFIG_BOOTFILE "uImage"
743 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
745 /* default location for tftp and bootm */
746 #define CONFIG_LOADADDR 1000000
749 #define CONFIG_BAUDRATE 115200
751 #define __USB_PHY_TYPE utmi
753 #define CONFIG_EXTRA_ENV_SETTINGS \
754 "hwconfig=fsl_ddr:bank_intlv=auto;" \
755 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
757 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
758 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
759 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
760 "tftpflash=tftpboot $loadaddr $uboot && " \
761 "protect off $ubootaddr +$filesize && " \
762 "erase $ubootaddr +$filesize && " \
763 "cp.b $loadaddr $ubootaddr $filesize && " \
764 "protect on $ubootaddr +$filesize && " \
765 "cmp.b $loadaddr $ubootaddr $filesize\0" \
766 "consoledev=ttyS0\0" \
767 "ramdiskaddr=2000000\0" \
768 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
769 "fdtaddr=1e00000\0" \
770 "fdtfile=t1040qds/t1040qds.dtb\0" \
773 #define CONFIG_LINUX \
774 "setenv bootargs root=/dev/ram rw " \
775 "console=$consoledev,$baudrate $othbootargs;" \
776 "setenv ramdiskaddr 0x02000000;" \
777 "setenv fdtaddr 0x00c00000;" \
778 "setenv loadaddr 0x1000000;" \
779 "bootm $loadaddr $ramdiskaddr $fdtaddr"
781 #define CONFIG_HDBOOT \
782 "setenv bootargs root=/dev/$bdev rw " \
783 "console=$consoledev,$baudrate $othbootargs;" \
784 "tftp $loadaddr $bootfile;" \
785 "tftp $fdtaddr $fdtfile;" \
786 "bootm $loadaddr - $fdtaddr"
788 #define CONFIG_NFSBOOTCOMMAND \
789 "setenv bootargs root=/dev/nfs rw " \
790 "nfsroot=$serverip:$rootpath " \
791 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
792 "console=$consoledev,$baudrate $othbootargs;" \
793 "tftp $loadaddr $bootfile;" \
794 "tftp $fdtaddr $fdtfile;" \
795 "bootm $loadaddr - $fdtaddr"
797 #define CONFIG_RAMBOOTCOMMAND \
798 "setenv bootargs root=/dev/ram rw " \
799 "console=$consoledev,$baudrate $othbootargs;" \
800 "tftp $ramdiskaddr $ramdiskfile;" \
801 "tftp $loadaddr $bootfile;" \
802 "tftp $fdtaddr $fdtfile;" \
803 "bootm $loadaddr $ramdiskaddr $fdtaddr"
805 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
807 #include <asm/fsl_secure_boot.h>
809 #endif /* __CONFIG_H */