2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * T1040 QDS board configuration file
29 #define CONFIG_T1040QDS
30 #define CONFIG_PHYS_64BIT
32 #ifdef CONFIG_RAMBOOT_PBL
33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
39 /* High Level Configuration Options */
41 #define CONFIG_E500 /* BOOKE e500 family */
42 #define CONFIG_E500MC /* BOOKE e500mc family */
43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
44 #define CONFIG_MP /* support multiple processors */
46 /* support deep sleep */
47 #define CONFIG_DEEP_SLEEP
48 #define CONFIG_SILENT_CONSOLE
50 #ifndef CONFIG_SYS_TEXT_BASE
51 #define CONFIG_SYS_TEXT_BASE 0xeff40000
54 #ifndef CONFIG_RESET_VECTOR_ADDRESS
55 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
58 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
59 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
60 #define CONFIG_FSL_IFC /* Enable IFC Support */
61 #define CONFIG_PCI /* Enable PCI/PCIE */
62 #define CONFIG_PCI_INDIRECT_BRIDGE
63 #define CONFIG_PCIE1 /* PCIE controler 1 */
64 #define CONFIG_PCIE2 /* PCIE controler 2 */
65 #define CONFIG_PCIE3 /* PCIE controler 3 */
66 #define CONFIG_PCIE4 /* PCIE controler 4 */
68 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
71 #define CONFIG_FSL_LAW /* Use common FSL init code */
73 #define CONFIG_ENV_OVERWRITE
75 #ifdef CONFIG_SYS_NO_FLASH
76 #define CONFIG_ENV_IS_NOWHERE
78 #define CONFIG_FLASH_CFI_DRIVER
79 #define CONFIG_SYS_FLASH_CFI
80 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
83 #ifndef CONFIG_SYS_NO_FLASH
84 #if defined(CONFIG_SPIFLASH)
85 #define CONFIG_SYS_EXTRA_ENV_RELOC
86 #define CONFIG_ENV_IS_IN_SPI_FLASH
87 #define CONFIG_ENV_SPI_BUS 0
88 #define CONFIG_ENV_SPI_CS 0
89 #define CONFIG_ENV_SPI_MAX_HZ 10000000
90 #define CONFIG_ENV_SPI_MODE 0
91 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
92 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
93 #define CONFIG_ENV_SECT_SIZE 0x10000
94 #elif defined(CONFIG_SDCARD)
95 #define CONFIG_SYS_EXTRA_ENV_RELOC
96 #define CONFIG_ENV_IS_IN_MMC
97 #define CONFIG_SYS_MMC_ENV_DEV 0
98 #define CONFIG_ENV_SIZE 0x2000
99 #define CONFIG_ENV_OFFSET (512 * 1658)
100 #elif defined(CONFIG_NAND)
101 #define CONFIG_SYS_EXTRA_ENV_RELOC
102 #define CONFIG_ENV_IS_IN_NAND
103 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
104 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
106 #define CONFIG_ENV_IS_IN_FLASH
107 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
108 #define CONFIG_ENV_SIZE 0x2000
109 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
111 #else /* CONFIG_SYS_NO_FLASH */
112 #define CONFIG_ENV_SIZE 0x2000
113 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
117 unsigned long get_board_sys_clk(void);
118 unsigned long get_board_ddr_clk(void);
121 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
122 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
125 * These can be toggled for performance analysis, otherwise use default.
127 #define CONFIG_SYS_CACHE_STASHING
128 #define CONFIG_BACKSIDE_L2_CACHE
129 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
130 #define CONFIG_BTB /* toggle branch predition */
131 #define CONFIG_DDR_ECC
132 #ifdef CONFIG_DDR_ECC
133 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
134 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
137 #define CONFIG_ENABLE_36BIT_PHYS
139 #define CONFIG_ADDR_MAP
140 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
142 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
143 #define CONFIG_SYS_MEMTEST_END 0x00400000
144 #define CONFIG_SYS_ALT_MEMTEST
145 #define CONFIG_PANIC_HANG /* do not reset board on panic */
148 * Config the L3 Cache as L3 SRAM
150 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
152 #define CONFIG_SYS_DCSRBAR 0xf0000000
153 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
156 #define CONFIG_ID_EEPROM
157 #define CONFIG_SYS_I2C_EEPROM_NXID
158 #define CONFIG_SYS_EEPROM_BUS_NUM 0
159 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
161 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
162 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
167 #define CONFIG_VERY_BIG_RAM
168 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
169 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
171 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
172 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
173 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
175 #define CONFIG_DDR_SPD
176 #ifndef CONFIG_SYS_FSL_DDR4
177 #define CONFIG_SYS_FSL_DDR3
178 #define CONFIG_FSL_DDR_INTERACTIVE
181 #define CONFIG_SYS_SPD_BUS_NUM 0
182 #define SPD_EEPROM_ADDRESS 0x51
184 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
189 #define CONFIG_SYS_FLASH_BASE 0xe0000000
190 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
192 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
193 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
195 CSPR_PORT_SIZE_16 | \
198 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
199 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
200 CSPR_PORT_SIZE_16 | \
203 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
208 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
210 /* NOR Flash Timing Params */
211 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
212 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
213 FTIM0_NOR_TEADC(0x5) | \
214 FTIM0_NOR_TEAHC(0x5))
215 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
216 FTIM1_NOR_TRAD_NOR(0x1A) |\
217 FTIM1_NOR_TSEQRAD_NOR(0x13))
218 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
219 FTIM2_NOR_TCH(0x4) | \
220 FTIM2_NOR_TWPH(0x0E) | \
222 #define CONFIG_SYS_NOR_FTIM3 0x0
224 #define CONFIG_SYS_FLASH_QUIET_TEST
225 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
227 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
228 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
229 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
230 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
232 #define CONFIG_SYS_FLASH_EMPTY_INFO
233 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
234 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
235 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
236 #define QIXIS_BASE 0xffdf0000
237 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
238 #define QIXIS_LBMAP_SWITCH 0x06
239 #define QIXIS_LBMAP_MASK 0x0f
240 #define QIXIS_LBMAP_SHIFT 0
241 #define QIXIS_LBMAP_DFLTBANK 0x00
242 #define QIXIS_LBMAP_ALTBANK 0x04
243 #define QIXIS_RST_CTL_RESET 0x31
244 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
245 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
246 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
247 #define QIXIS_RST_FORCE_MEM 0x01
249 #define CONFIG_SYS_CSPR3_EXT (0xf)
250 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
254 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
255 #define CONFIG_SYS_CSOR3 0x0
256 /* QIXIS Timing parameters for IFC CS3 */
257 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
258 FTIM0_GPCM_TEADC(0x0e) | \
259 FTIM0_GPCM_TEAHC(0x0e))
260 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
261 FTIM1_GPCM_TRAD(0x3f))
262 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
263 FTIM2_GPCM_TCH(0x8) | \
264 FTIM2_GPCM_TWP(0x1f))
265 #define CONFIG_SYS_CS3_FTIM3 0x0
267 #define CONFIG_NAND_FSL_IFC
268 #define CONFIG_SYS_NAND_BASE 0xff800000
269 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
271 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
272 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
273 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
274 | CSPR_MSEL_NAND /* MSEL = NAND */ \
276 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
278 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
279 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
280 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
281 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
282 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
283 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
284 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
286 #define CONFIG_SYS_NAND_ONFI_DETECTION
288 /* ONFI NAND Flash mode0 Timing Params */
289 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
290 FTIM0_NAND_TWP(0x18) | \
291 FTIM0_NAND_TWCHT(0x07) | \
292 FTIM0_NAND_TWH(0x0a))
293 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
294 FTIM1_NAND_TWBE(0x39) | \
295 FTIM1_NAND_TRR(0x0e) | \
296 FTIM1_NAND_TRP(0x18))
297 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
298 FTIM2_NAND_TREH(0x0a) | \
299 FTIM2_NAND_TWHRE(0x1e))
300 #define CONFIG_SYS_NAND_FTIM3 0x0
302 #define CONFIG_SYS_NAND_DDR_LAW 11
303 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
304 #define CONFIG_SYS_MAX_NAND_DEVICE 1
305 #define CONFIG_MTD_NAND_VERIFY_WRITE
306 #define CONFIG_CMD_NAND
308 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
310 #if defined(CONFIG_NAND)
311 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
312 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
313 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
314 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
315 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
316 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
317 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
318 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
319 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
320 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
321 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
322 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
323 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
324 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
325 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
326 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
327 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
328 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
329 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
330 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
331 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
332 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
333 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
334 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
336 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
337 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
338 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
339 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
340 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
341 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
342 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
343 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
344 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
345 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
346 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
347 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
348 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
349 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
350 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
351 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
352 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
353 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
354 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
355 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
356 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
357 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
358 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
359 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
362 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
364 #if defined(CONFIG_RAMBOOT_PBL)
365 #define CONFIG_SYS_RAMBOOT
368 #define CONFIG_BOARD_EARLY_INIT_R
369 #define CONFIG_MISC_INIT_R
371 #define CONFIG_HWCONFIG
373 /* define to use L1 as initial stack */
374 #define CONFIG_L1_INIT_RAM
375 #define CONFIG_SYS_INIT_RAM_LOCK
376 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
377 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
379 /* The assembler doesn't like typecast */
380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
381 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
382 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
383 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
385 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
386 GENERATED_GBL_DATA_SIZE)
387 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
389 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
390 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
392 /* Serial Port - controlled on board with jumper J8
396 #define CONFIG_CONS_INDEX 1
397 #define CONFIG_SYS_NS16550
398 #define CONFIG_SYS_NS16550_SERIAL
399 #define CONFIG_SYS_NS16550_REG_SIZE 1
400 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
402 #define CONFIG_SYS_BAUDRATE_TABLE \
403 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
405 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
406 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
407 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
408 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
409 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
410 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
412 /* Use the HUSH parser */
413 #define CONFIG_SYS_HUSH_PARSER
414 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
417 #define CONFIG_FSL_DIU_FB
418 #ifdef CONFIG_FSL_DIU_FB
419 #define CONFIG_FSL_DIU_CH7301
420 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
422 #define CONFIG_CMD_BMP
423 #define CONFIG_CFB_CONSOLE
424 #define CONFIG_VIDEO_SW_CURSOR
425 #define CONFIG_VGA_AS_SINGLE_DEVICE
426 #define CONFIG_VIDEO_LOGO
427 #define CONFIG_VIDEO_BMP_LOGO
428 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
430 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
431 * disable empty flash sector detection, which is I/O-intensive.
433 #undef CONFIG_SYS_FLASH_EMPTY_INFO
436 /* pass open firmware flat tree */
437 #define CONFIG_OF_LIBFDT
438 #define CONFIG_OF_BOARD_SETUP
439 #define CONFIG_OF_STDOUT_VIA_ALIAS
441 /* new uImage format support */
443 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
446 #define CONFIG_SYS_I2C
447 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
448 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
449 #define CONFIG_SYS_FSL_I2C2_SPEED 50000
450 #define CONFIG_SYS_FSL_I2C3_SPEED 50000
451 #define CONFIG_SYS_FSL_I2C4_SPEED 50000
452 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
453 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
454 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
455 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
456 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
457 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
458 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
459 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
461 #define I2C_MUX_PCA_ADDR 0x77
462 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
465 /* I2C bus multiplexer */
466 #define I2C_MUX_CH_DEFAULT 0x8
467 #define I2C_MUX_CH_DIU 0xC
469 /* LDI/DVI Encoder for display */
470 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
471 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
477 #define CONFIG_RTC_DS3231 1
478 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
481 * eSPI - Enhanced SPI
483 #define CONFIG_FSL_ESPI
484 #define CONFIG_SPI_FLASH
485 #define CONFIG_SPI_FLASH_STMICRO
486 #define CONFIG_SPI_FLASH_SST
487 #define CONFIG_SPI_FLASH_EON
488 #define CONFIG_CMD_SF
489 #define CONFIG_SF_DEFAULT_SPEED 10000000
490 #define CONFIG_SF_DEFAULT_MODE 0
494 * Memory space is mapped 1-1, but I/O space must start from 0.
498 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
500 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
501 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
502 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
503 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
504 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
505 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
506 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
507 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
510 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
512 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
513 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
514 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
515 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
516 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
517 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
518 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
519 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
522 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
524 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
525 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
526 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
527 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
528 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
529 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
530 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
531 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
534 /* controller 4, Base address 203000 */
536 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
537 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
538 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
539 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
540 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
541 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
542 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
543 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
546 #define CONFIG_PCI_PNP /* do pci plug-and-play */
549 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
550 #define CONFIG_DOS_PARTITION
551 #endif /* CONFIG_PCI */
554 #define CONFIG_FSL_SATA_V2
555 #ifdef CONFIG_FSL_SATA_V2
556 #define CONFIG_LIBATA
557 #define CONFIG_FSL_SATA
559 #define CONFIG_SYS_SATA_MAX_DEVICE 2
561 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
562 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
564 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
565 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
568 #define CONFIG_CMD_SATA
569 #define CONFIG_DOS_PARTITION
570 #define CONFIG_CMD_EXT2
576 #define CONFIG_HAS_FSL_DR_USB
578 #ifdef CONFIG_HAS_FSL_DR_USB
579 #define CONFIG_USB_EHCI
581 #ifdef CONFIG_USB_EHCI
582 #define CONFIG_CMD_USB
583 #define CONFIG_USB_STORAGE
584 #define CONFIG_USB_EHCI_FSL
585 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
586 #define CONFIG_CMD_EXT2
593 #define CONFIG_FSL_ESDHC
594 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
595 #define CONFIG_CMD_MMC
596 #define CONFIG_GENERIC_MMC
597 #define CONFIG_CMD_EXT2
598 #define CONFIG_CMD_FAT
599 #define CONFIG_DOS_PARTITION
603 #ifndef CONFIG_NOBQFMAN
604 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
605 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
606 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
607 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
608 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
609 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
610 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
611 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
612 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
614 #define CONFIG_SYS_DPAA_FMAN
615 #define CONFIG_SYS_DPAA_PME
619 /* Default address of microcode for the Linux Fman driver */
620 #if defined(CONFIG_SPIFLASH)
622 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
623 * env, so we got 0x110000.
625 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
626 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
627 #elif defined(CONFIG_SDCARD)
629 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
630 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
631 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
633 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
634 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
635 #elif defined(CONFIG_NAND)
636 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
637 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
639 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
640 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
641 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
643 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
644 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
645 #endif /* CONFIG_NOBQFMAN */
647 #ifdef CONFIG_SYS_DPAA_FMAN
648 #define CONFIG_FMAN_ENET
649 #define CONFIG_PHYLIB_10G
650 #define CONFIG_PHY_VITESSE
651 #define CONFIG_PHY_REALTEK
652 #define CONFIG_PHY_TERANETICS
653 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
654 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
655 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
656 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
659 #ifdef CONFIG_FMAN_ENET
660 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
661 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
663 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
664 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
665 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
666 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
668 #define CONFIG_MII /* MII PHY management */
669 #define CONFIG_ETHPRIME "FM1@DTSEC1"
670 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
674 * Dynamic MTD Partition support with mtdparts
676 #ifndef CONFIG_SYS_NO_FLASH
677 #define CONFIG_MTD_DEVICE
678 #define CONFIG_MTD_PARTITIONS
679 #define CONFIG_CMD_MTDPARTS
680 #define CONFIG_FLASH_CFI_MTD
681 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
683 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
684 "128k(dtb),96m(fs),-(user);"\
685 "fff800000.flash:2m(uboot),9m(kernel),"\
686 "128k(dtb),96m(fs),-(user);spife110000.0:" \
687 "2m(uboot),9m(kernel),128k(dtb),-(user)"
693 #define CONFIG_LOADS_ECHO /* echo on for serial download */
694 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
697 * Command line configuration.
699 #include <config_cmd_default.h>
701 #define CONFIG_CMD_DATE
702 #define CONFIG_CMD_DHCP
703 #define CONFIG_CMD_EEPROM
704 #define CONFIG_CMD_ELF
705 #define CONFIG_CMD_ERRATA
706 #define CONFIG_CMD_GREPENV
707 #define CONFIG_CMD_IRQ
708 #define CONFIG_CMD_I2C
709 #define CONFIG_CMD_MII
710 #define CONFIG_CMD_PING
711 #define CONFIG_CMD_REGINFO
712 #define CONFIG_CMD_SETEXPR
715 #define CONFIG_CMD_PCI
716 #define CONFIG_CMD_NET
720 * Miscellaneous configurable options
722 #define CONFIG_SYS_LONGHELP /* undef to save memory */
723 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
724 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
725 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
726 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
727 #ifdef CONFIG_CMD_KGDB
728 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
730 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
732 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
733 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
734 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
737 * For booting Linux, the board info and command line data
738 * have to be in the first 64 MB of memory, since this is
739 * the maximum mapped by the Linux kernel during initialization.
741 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
742 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
744 #ifdef CONFIG_CMD_KGDB
745 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
749 * Environment Configuration
751 #define CONFIG_ROOTPATH "/opt/nfsroot"
752 #define CONFIG_BOOTFILE "uImage"
753 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
755 /* default location for tftp and bootm */
756 #define CONFIG_LOADADDR 1000000
758 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
760 #define CONFIG_BAUDRATE 115200
762 #define __USB_PHY_TYPE utmi
764 #define CONFIG_EXTRA_ENV_SETTINGS \
765 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
766 "bank_intlv=cs0_cs1;" \
767 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
769 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
770 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
771 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
772 "tftpflash=tftpboot $loadaddr $uboot && " \
773 "protect off $ubootaddr +$filesize && " \
774 "erase $ubootaddr +$filesize && " \
775 "cp.b $loadaddr $ubootaddr $filesize && " \
776 "protect on $ubootaddr +$filesize && " \
777 "cmp.b $loadaddr $ubootaddr $filesize\0" \
778 "consoledev=ttyS0\0" \
779 "ramdiskaddr=2000000\0" \
780 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
782 "fdtfile=t1040qds/t1040qds.dtb\0" \
785 #define CONFIG_LINUX \
786 "setenv bootargs root=/dev/ram rw " \
787 "console=$consoledev,$baudrate $othbootargs;" \
788 "setenv ramdiskaddr 0x02000000;" \
789 "setenv fdtaddr 0x00c00000;" \
790 "setenv loadaddr 0x1000000;" \
791 "bootm $loadaddr $ramdiskaddr $fdtaddr"
793 #define CONFIG_HDBOOT \
794 "setenv bootargs root=/dev/$bdev rw " \
795 "console=$consoledev,$baudrate $othbootargs;" \
796 "tftp $loadaddr $bootfile;" \
797 "tftp $fdtaddr $fdtfile;" \
798 "bootm $loadaddr - $fdtaddr"
800 #define CONFIG_NFSBOOTCOMMAND \
801 "setenv bootargs root=/dev/nfs rw " \
802 "nfsroot=$serverip:$rootpath " \
803 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
804 "console=$consoledev,$baudrate $othbootargs;" \
805 "tftp $loadaddr $bootfile;" \
806 "tftp $fdtaddr $fdtfile;" \
807 "bootm $loadaddr - $fdtaddr"
809 #define CONFIG_RAMBOOTCOMMAND \
810 "setenv bootargs root=/dev/ram rw " \
811 "console=$consoledev,$baudrate $othbootargs;" \
812 "tftp $ramdiskaddr $ramdiskfile;" \
813 "tftp $loadaddr $bootfile;" \
814 "tftp $fdtaddr $fdtfile;" \
815 "bootm $loadaddr $ramdiskaddr $fdtaddr"
817 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
819 #ifdef CONFIG_SECURE_BOOT
820 #include <asm/fsl_secure_boot.h>
823 #endif /* __CONFIG_H */