2 + * Copyright 2014 Freescale Semiconductor, Inc.
4 + * SPDX-License-Identifier: GPL-2.0+
11 * T104x RDB board configuration file
13 #define CONFIG_T104xRDB
14 #define CONFIG_PHYS_64BIT
15 #define CONFIG_SYS_GENERIC_BOARD
16 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_E500 /* BOOKE e500 family */
19 #include <asm/config_mpc85xx.h>
21 #ifdef CONFIG_RAMBOOT_PBL
22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
23 #ifdef CONFIG_T1040RDB
24 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
26 #ifdef CONFIG_T1042RDB_PI
27 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
29 #ifdef CONFIG_T1042RDB
30 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
33 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
34 #define CONFIG_SPL_ENV_SUPPORT
35 #define CONFIG_SPL_SERIAL_SUPPORT
36 #define CONFIG_SPL_FLUSH_IMAGE
37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
38 #define CONFIG_SPL_LIBGENERIC_SUPPORT
39 #define CONFIG_SPL_LIBCOMMON_SUPPORT
40 #define CONFIG_SPL_I2C_SUPPORT
41 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
42 #define CONFIG_FSL_LAW /* Use common FSL init code */
43 #define CONFIG_SYS_TEXT_BASE 0x30001000
44 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
45 #define CONFIG_SPL_PAD_TO 0x40000
46 #define CONFIG_SPL_MAX_SIZE 0x28000
47 #ifdef CONFIG_SPL_BUILD
48 #define CONFIG_SPL_SKIP_RELOCATE
49 #define CONFIG_SPL_COMMON_INIT_DDR
50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
51 #define CONFIG_SYS_NO_FLASH
53 #define RESET_VECTOR_OFFSET 0x27FFC
54 #define BOOT_PAGE_OFFSET 0x27000
57 #define CONFIG_SPL_NAND_SUPPORT
58 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
59 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
60 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
61 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
62 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
63 #define CONFIG_SPL_NAND_BOOT
66 #ifdef CONFIG_SPIFLASH
67 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
68 #define CONFIG_SPL_SPI_SUPPORT
69 #define CONFIG_SPL_SPI_FLASH_SUPPORT
70 #define CONFIG_SPL_SPI_FLASH_MINIMAL
71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
76 #ifndef CONFIG_SPL_BUILD
77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
79 #define CONFIG_SPL_SPI_BOOT
83 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
84 #define CONFIG_SPL_MMC_SUPPORT
85 #define CONFIG_SPL_MMC_MINIMAL
86 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
87 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
88 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
89 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
91 #ifndef CONFIG_SPL_BUILD
92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
94 #define CONFIG_SPL_MMC_BOOT
99 /* High Level Configuration Options */
101 #define CONFIG_E500MC /* BOOKE e500mc family */
102 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
103 #define CONFIG_MP /* support multiple processors */
105 /* support deep sleep */
106 #define CONFIG_DEEP_SLEEP
107 #define CONFIG_SILENT_CONSOLE
109 #ifndef CONFIG_SYS_TEXT_BASE
110 #define CONFIG_SYS_TEXT_BASE 0xeff40000
113 #ifndef CONFIG_RESET_VECTOR_ADDRESS
114 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
117 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
118 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
119 #define CONFIG_FSL_IFC /* Enable IFC Support */
120 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
121 #define CONFIG_PCI /* Enable PCI/PCIE */
122 #define CONFIG_PCI_INDIRECT_BRIDGE
123 #define CONFIG_PCIE1 /* PCIE controler 1 */
124 #define CONFIG_PCIE2 /* PCIE controler 2 */
125 #define CONFIG_PCIE3 /* PCIE controler 3 */
126 #define CONFIG_PCIE4 /* PCIE controler 4 */
128 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
129 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
131 #define CONFIG_FSL_LAW /* Use common FSL init code */
133 #define CONFIG_ENV_OVERWRITE
135 #ifndef CONFIG_SYS_NO_FLASH
136 #define CONFIG_FLASH_CFI_DRIVER
137 #define CONFIG_SYS_FLASH_CFI
138 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
141 #if defined(CONFIG_SPIFLASH)
142 #define CONFIG_SYS_EXTRA_ENV_RELOC
143 #define CONFIG_ENV_IS_IN_SPI_FLASH
144 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
145 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
146 #define CONFIG_ENV_SECT_SIZE 0x10000
147 #elif defined(CONFIG_SDCARD)
148 #define CONFIG_SYS_EXTRA_ENV_RELOC
149 #define CONFIG_ENV_IS_IN_MMC
150 #define CONFIG_SYS_MMC_ENV_DEV 0
151 #define CONFIG_ENV_SIZE 0x2000
152 #define CONFIG_ENV_OFFSET (512 * 0x800)
153 #elif defined(CONFIG_NAND)
154 #define CONFIG_SYS_EXTRA_ENV_RELOC
155 #define CONFIG_ENV_IS_IN_NAND
156 #define CONFIG_ENV_SIZE 0x2000
157 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
159 #define CONFIG_ENV_IS_IN_FLASH
160 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
161 #define CONFIG_ENV_SIZE 0x2000
162 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
165 #define CONFIG_SYS_CLK_FREQ 100000000
166 #define CONFIG_DDR_CLK_FREQ 66666666
169 * These can be toggled for performance analysis, otherwise use default.
171 #define CONFIG_SYS_CACHE_STASHING
172 #define CONFIG_BACKSIDE_L2_CACHE
173 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
174 #define CONFIG_BTB /* toggle branch predition */
175 #define CONFIG_DDR_ECC
176 #ifdef CONFIG_DDR_ECC
177 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
178 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
181 #define CONFIG_ENABLE_36BIT_PHYS
183 #define CONFIG_ADDR_MAP
184 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
186 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
187 #define CONFIG_SYS_MEMTEST_END 0x00400000
188 #define CONFIG_SYS_ALT_MEMTEST
189 #define CONFIG_PANIC_HANG /* do not reset board on panic */
192 * Config the L3 Cache as L3 SRAM
194 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
195 #define CONFIG_SYS_L3_SIZE 256 << 10
196 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
197 #ifdef CONFIG_RAMBOOT_PBL
198 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
200 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
201 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
202 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
203 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
205 #define CONFIG_SYS_DCSRBAR 0xf0000000
206 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
211 #define CONFIG_VERY_BIG_RAM
212 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
213 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
215 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
216 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
217 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
219 #define CONFIG_DDR_SPD
220 #define CONFIG_SYS_DDR_RAW_TIMING
221 #define CONFIG_SYS_FSL_DDR3
223 #define CONFIG_SYS_SPD_BUS_NUM 0
224 #define SPD_EEPROM_ADDRESS 0x51
226 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
231 #define CONFIG_SYS_FLASH_BASE 0xe8000000
232 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
234 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
235 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
236 CSPR_PORT_SIZE_16 | \
239 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
244 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
246 /* NOR Flash Timing Params */
247 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
248 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
249 FTIM0_NOR_TEADC(0x5) | \
250 FTIM0_NOR_TEAHC(0x5))
251 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
252 FTIM1_NOR_TRAD_NOR(0x1A) |\
253 FTIM1_NOR_TSEQRAD_NOR(0x13))
254 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
255 FTIM2_NOR_TCH(0x4) | \
256 FTIM2_NOR_TWPH(0x0E) | \
258 #define CONFIG_SYS_NOR_FTIM3 0x0
260 #define CONFIG_SYS_FLASH_QUIET_TEST
261 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
263 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
264 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
265 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
266 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
268 #define CONFIG_SYS_FLASH_EMPTY_INFO
269 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
272 #define CPLD_LBMAP_MASK 0x3F
273 #define CPLD_BANK_SEL_MASK 0x07
274 #define CPLD_BANK_OVERRIDE 0x40
275 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
276 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
277 #define CPLD_LBMAP_RESET 0xFF
278 #define CPLD_LBMAP_SHIFT 0x03
279 #ifdef CONFIG_T1042RDB_PI
280 #define CPLD_DIU_SEL_DFP 0x80
283 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
284 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
285 #define CONFIG_SYS_CSPR2_EXT (0xf)
286 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
290 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
291 #define CONFIG_SYS_CSOR2 0x0
292 /* CPLD Timing parameters for IFC CS2 */
293 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
294 FTIM0_GPCM_TEADC(0x0e) | \
295 FTIM0_GPCM_TEAHC(0x0e))
296 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
297 FTIM1_GPCM_TRAD(0x1f))
298 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
299 FTIM2_GPCM_TCH(0x8) | \
300 FTIM2_GPCM_TWP(0x1f))
301 #define CONFIG_SYS_CS2_FTIM3 0x0
303 /* NAND Flash on IFC */
304 #define CONFIG_NAND_FSL_IFC
305 #define CONFIG_SYS_NAND_BASE 0xff800000
306 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
308 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
309 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
310 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
311 | CSPR_MSEL_NAND /* MSEL = NAND */ \
313 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
315 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
316 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
317 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
318 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
319 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
320 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
321 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
323 #define CONFIG_SYS_NAND_ONFI_DETECTION
325 /* ONFI NAND Flash mode0 Timing Params */
326 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
327 FTIM0_NAND_TWP(0x18) | \
328 FTIM0_NAND_TWCHT(0x07) | \
329 FTIM0_NAND_TWH(0x0a))
330 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
331 FTIM1_NAND_TWBE(0x39) | \
332 FTIM1_NAND_TRR(0x0e) | \
333 FTIM1_NAND_TRP(0x18))
334 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
335 FTIM2_NAND_TREH(0x0a) | \
336 FTIM2_NAND_TWHRE(0x1e))
337 #define CONFIG_SYS_NAND_FTIM3 0x0
339 #define CONFIG_SYS_NAND_DDR_LAW 11
340 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
341 #define CONFIG_SYS_MAX_NAND_DEVICE 1
342 #define CONFIG_MTD_NAND_VERIFY_WRITE
343 #define CONFIG_CMD_NAND
345 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
347 #if defined(CONFIG_NAND)
348 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
349 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
350 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
351 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
352 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
353 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
354 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
355 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
356 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
357 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
358 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
359 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
360 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
361 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
362 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
363 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
365 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
366 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
367 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
368 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
369 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
370 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
371 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
372 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
373 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
374 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
375 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
376 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
377 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
378 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
379 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
380 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
383 #ifdef CONFIG_SPL_BUILD
384 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
386 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
389 #if defined(CONFIG_RAMBOOT_PBL)
390 #define CONFIG_SYS_RAMBOOT
393 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
394 #if defined(CONFIG_NAND)
395 #define CONFIG_A008044_WORKAROUND
399 #define CONFIG_BOARD_EARLY_INIT_R
400 #define CONFIG_MISC_INIT_R
402 #define CONFIG_HWCONFIG
404 /* define to use L1 as initial stack */
405 #define CONFIG_L1_INIT_RAM
406 #define CONFIG_SYS_INIT_RAM_LOCK
407 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
408 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
409 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
410 /* The assembler doesn't like typecast */
411 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
412 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
413 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
414 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
416 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
417 GENERATED_GBL_DATA_SIZE)
418 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
420 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
421 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
423 /* Serial Port - controlled on board with jumper J8
427 #define CONFIG_CONS_INDEX 1
428 #define CONFIG_SYS_NS16550
429 #define CONFIG_SYS_NS16550_SERIAL
430 #define CONFIG_SYS_NS16550_REG_SIZE 1
431 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
433 #define CONFIG_SYS_BAUDRATE_TABLE \
434 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
436 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
437 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
438 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
439 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
440 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
441 #ifndef CONFIG_SPL_BUILD
442 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
445 /* Use the HUSH parser */
446 #define CONFIG_SYS_HUSH_PARSER
447 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
449 #ifdef CONFIG_T1042RDB_PI
451 #define CONFIG_FSL_DIU_FB
453 #ifdef CONFIG_FSL_DIU_FB
454 #define CONFIG_FSL_DIU_CH7301
455 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
457 #define CONFIG_CMD_BMP
458 #define CONFIG_CFB_CONSOLE
459 #define CONFIG_CFB_CONSOLE_ANSI
460 #define CONFIG_VIDEO_SW_CURSOR
461 #define CONFIG_VGA_AS_SINGLE_DEVICE
462 #define CONFIG_VIDEO_LOGO
463 #define CONFIG_VIDEO_BMP_LOGO
467 /* pass open firmware flat tree */
468 #define CONFIG_OF_LIBFDT
469 #define CONFIG_OF_BOARD_SETUP
470 #define CONFIG_OF_STDOUT_VIA_ALIAS
472 /* new uImage format support */
474 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
477 #define CONFIG_SYS_I2C
478 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
479 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
480 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
481 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
482 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
483 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
484 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
485 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
486 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
487 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
488 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
489 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
490 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
492 /* I2C bus multiplexer */
493 #define I2C_MUX_PCA_ADDR 0x70
494 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
495 #define I2C_MUX_CH_DEFAULT 0x8
498 #ifdef CONFIG_T1042RDB_PI
499 /* LDI/DVI Encoder for display */
500 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
501 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
507 #define CONFIG_RTC_DS1337 1
508 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
511 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
515 * eSPI - Enhanced SPI
517 #define CONFIG_FSL_ESPI
518 #define CONFIG_SPI_FLASH
519 #define CONFIG_SPI_FLASH_STMICRO
520 #define CONFIG_SPI_FLASH_BAR
521 #define CONFIG_CMD_SF
522 #define CONFIG_SF_DEFAULT_SPEED 10000000
523 #define CONFIG_SF_DEFAULT_MODE 0
524 #define CONFIG_ENV_SPI_BUS 0
525 #define CONFIG_ENV_SPI_CS 0
526 #define CONFIG_ENV_SPI_MAX_HZ 10000000
527 #define CONFIG_ENV_SPI_MODE 0
531 * Memory space is mapped 1-1, but I/O space must start from 0.
535 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
537 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
538 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
539 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
540 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
541 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
542 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
543 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
544 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
547 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
549 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
550 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
551 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
552 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
553 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
554 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
555 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
556 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
559 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
561 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
562 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
563 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
564 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
565 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
566 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
567 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
568 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
571 /* controller 4, Base address 203000 */
573 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
574 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
575 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
576 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
577 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
578 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
579 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
580 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
583 #define CONFIG_PCI_PNP /* do pci plug-and-play */
586 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
587 #define CONFIG_DOS_PARTITION
588 #endif /* CONFIG_PCI */
591 #define CONFIG_FSL_SATA_V2
592 #ifdef CONFIG_FSL_SATA_V2
593 #define CONFIG_LIBATA
594 #define CONFIG_FSL_SATA
596 #define CONFIG_SYS_SATA_MAX_DEVICE 1
598 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
599 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
602 #define CONFIG_CMD_SATA
603 #define CONFIG_DOS_PARTITION
604 #define CONFIG_CMD_EXT2
610 #define CONFIG_HAS_FSL_DR_USB
612 #ifdef CONFIG_HAS_FSL_DR_USB
613 #define CONFIG_USB_EHCI
615 #ifdef CONFIG_USB_EHCI
616 #define CONFIG_CMD_USB
617 #define CONFIG_USB_STORAGE
618 #define CONFIG_USB_EHCI_FSL
619 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
620 #define CONFIG_CMD_EXT2
627 #define CONFIG_FSL_ESDHC
628 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
629 #define CONFIG_CMD_MMC
630 #define CONFIG_GENERIC_MMC
631 #define CONFIG_CMD_EXT2
632 #define CONFIG_CMD_FAT
633 #define CONFIG_DOS_PARTITION
637 #ifndef CONFIG_NOBQFMAN
638 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
639 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
640 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
641 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
642 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
643 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
644 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
645 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
646 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
648 #define CONFIG_SYS_DPAA_FMAN
649 #define CONFIG_SYS_DPAA_PME
651 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
656 /* Default address of microcode for the Linux Fman driver */
657 #if defined(CONFIG_SPIFLASH)
659 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
660 * env, so we got 0x110000.
662 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
663 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
664 #elif defined(CONFIG_SDCARD)
666 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
667 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
668 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
670 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
671 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
672 #elif defined(CONFIG_NAND)
673 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
674 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
676 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
677 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
680 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
681 #if defined(CONFIG_SPIFLASH)
682 #define CONFIG_SYS_QE_FW_ADDR 0x130000
683 #elif defined(CONFIG_SDCARD)
684 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
685 #elif defined(CONFIG_NAND)
686 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
688 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
693 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
694 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
695 #endif /* CONFIG_NOBQFMAN */
697 #ifdef CONFIG_SYS_DPAA_FMAN
698 #define CONFIG_FMAN_ENET
699 #define CONFIG_PHY_VITESSE
700 #define CONFIG_PHY_REALTEK
703 #ifdef CONFIG_FMAN_ENET
704 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
705 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
707 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
708 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
710 #define CONFIG_MII /* MII PHY management */
711 #define CONFIG_ETHPRIME "FM1@DTSEC4"
712 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
718 #define CONFIG_LOADS_ECHO /* echo on for serial download */
719 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
722 * Command line configuration.
724 #include <config_cmd_default.h>
726 #ifdef CONFIG_T1042RDB_PI
727 #define CONFIG_CMD_DATE
729 #define CONFIG_CMD_DHCP
730 #define CONFIG_CMD_ELF
731 #define CONFIG_CMD_ERRATA
732 #define CONFIG_CMD_GREPENV
733 #define CONFIG_CMD_IRQ
734 #define CONFIG_CMD_I2C
735 #define CONFIG_CMD_MII
736 #define CONFIG_CMD_PING
737 #define CONFIG_CMD_REGINFO
738 #define CONFIG_CMD_SETEXPR
741 #define CONFIG_CMD_PCI
742 #define CONFIG_CMD_NET
745 /* Hash command with SHA acceleration supported in hardware */
746 #ifdef CONFIG_FSL_CAAM
747 #define CONFIG_CMD_HASH
748 #define CONFIG_SHA_HW_ACCEL
752 * Miscellaneous configurable options
754 #define CONFIG_SYS_LONGHELP /* undef to save memory */
755 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
756 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
757 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
758 #ifdef CONFIG_CMD_KGDB
759 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
761 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
763 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
764 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
765 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
768 * For booting Linux, the board info and command line data
769 * have to be in the first 64 MB of memory, since this is
770 * the maximum mapped by the Linux kernel during initialization.
772 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
773 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
775 #ifdef CONFIG_CMD_KGDB
776 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
780 * Dynamic MTD Partition support with mtdparts
782 #ifndef CONFIG_SYS_NO_FLASH
783 #define CONFIG_MTD_DEVICE
784 #define CONFIG_MTD_PARTITIONS
785 #define CONFIG_CMD_MTDPARTS
786 #define CONFIG_FLASH_CFI_MTD
787 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
789 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
790 "128k(dtb),96m(fs),-(user);"\
791 "fff800000.flash:2m(uboot),9m(kernel),"\
792 "128k(dtb),96m(fs),-(user);spife110000.0:" \
793 "2m(uboot),9m(kernel),128k(dtb),-(user)"
797 * Environment Configuration
799 #define CONFIG_ROOTPATH "/opt/nfsroot"
800 #define CONFIG_BOOTFILE "uImage"
801 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
803 /* default location for tftp and bootm */
804 #define CONFIG_LOADADDR 1000000
806 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
808 #define CONFIG_BAUDRATE 115200
810 #define __USB_PHY_TYPE utmi
811 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
813 #ifdef CONFIG_T1040RDB
814 #define FDTFILE "t1040rdb/t1040rdb.dtb"
815 #elif defined(CONFIG_T1042RDB_PI)
816 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
817 #elif defined(CONFIG_T1042RDB)
818 #define FDTFILE "t1042rdb/t1042rdb.dtb"
821 #ifdef CONFIG_FSL_DIU_FB
822 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
824 #define DIU_ENVIRONMENT
827 #define CONFIG_EXTRA_ENV_SETTINGS \
828 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
829 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
830 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
832 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
833 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
834 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
835 "tftpflash=tftpboot $loadaddr $uboot && " \
836 "protect off $ubootaddr +$filesize && " \
837 "erase $ubootaddr +$filesize && " \
838 "cp.b $loadaddr $ubootaddr $filesize && " \
839 "protect on $ubootaddr +$filesize && " \
840 "cmp.b $loadaddr $ubootaddr $filesize\0" \
841 "consoledev=ttyS0\0" \
842 "ramdiskaddr=2000000\0" \
843 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
845 "fdtfile=" __stringify(FDTFILE) "\0" \
848 #define CONFIG_LINUX \
849 "setenv bootargs root=/dev/ram rw " \
850 "console=$consoledev,$baudrate $othbootargs;" \
851 "setenv ramdiskaddr 0x02000000;" \
852 "setenv fdtaddr 0x00c00000;" \
853 "setenv loadaddr 0x1000000;" \
854 "bootm $loadaddr $ramdiskaddr $fdtaddr"
856 #define CONFIG_HDBOOT \
857 "setenv bootargs root=/dev/$bdev rw " \
858 "console=$consoledev,$baudrate $othbootargs;" \
859 "tftp $loadaddr $bootfile;" \
860 "tftp $fdtaddr $fdtfile;" \
861 "bootm $loadaddr - $fdtaddr"
863 #define CONFIG_NFSBOOTCOMMAND \
864 "setenv bootargs root=/dev/nfs rw " \
865 "nfsroot=$serverip:$rootpath " \
866 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
867 "console=$consoledev,$baudrate $othbootargs;" \
868 "tftp $loadaddr $bootfile;" \
869 "tftp $fdtaddr $fdtfile;" \
870 "bootm $loadaddr - $fdtaddr"
872 #define CONFIG_RAMBOOTCOMMAND \
873 "setenv bootargs root=/dev/ram rw " \
874 "console=$consoledev,$baudrate $othbootargs;" \
875 "tftp $ramdiskaddr $ramdiskfile;" \
876 "tftp $loadaddr $bootfile;" \
877 "tftp $fdtaddr $fdtfile;" \
878 "bootm $loadaddr $ramdiskaddr $fdtaddr"
880 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
882 #ifdef CONFIG_SECURE_BOOT
883 #include <asm/fsl_secure_boot.h>
884 #define CONFIG_CMD_BLOB
887 #endif /* __CONFIG_H */