2 + * Copyright 2014 Freescale Semiconductor, Inc.
4 + * SPDX-License-Identifier: GPL-2.0+
11 * T104x RDB board configuration file
13 #define CONFIG_T104xRDB
14 #define CONFIG_DISPLAY_BOARDINFO
16 #define CONFIG_E500 /* BOOKE e500 family */
17 #include <asm/config_mpc85xx.h>
19 #ifdef CONFIG_RAMBOOT_PBL
21 #ifndef CONFIG_SECURE_BOOT
22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
24 #define CONFIG_SYS_FSL_PBL_PBI \
25 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
28 #ifdef CONFIG_T1040RDB
29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
31 #ifdef CONFIG_T1042RDB_PI
32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
34 #ifdef CONFIG_T1042RDB
35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
37 #ifdef CONFIG_T1040D4RDB
38 #define CONFIG_SYS_FSL_PBL_RCW \
39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
41 #ifdef CONFIG_T1042D4RDB
42 #define CONFIG_SYS_FSL_PBL_RCW \
43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
47 #define CONFIG_SPL_SERIAL_SUPPORT
48 #define CONFIG_SPL_FLUSH_IMAGE
49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
50 #define CONFIG_SPL_LIBGENERIC_SUPPORT
51 #define CONFIG_SPL_LIBCOMMON_SUPPORT
52 #define CONFIG_FSL_LAW /* Use common FSL init code */
53 #define CONFIG_SYS_TEXT_BASE 0x30001000
54 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
55 #define CONFIG_SPL_PAD_TO 0x40000
56 #define CONFIG_SPL_MAX_SIZE 0x28000
57 #ifdef CONFIG_SPL_BUILD
58 #define CONFIG_SPL_SKIP_RELOCATE
59 #define CONFIG_SPL_COMMON_INIT_DDR
60 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
61 #define CONFIG_SYS_NO_FLASH
63 #define RESET_VECTOR_OFFSET 0x27FFC
64 #define BOOT_PAGE_OFFSET 0x27000
67 #define CONFIG_SPL_NAND_SUPPORT
68 #ifdef CONFIG_SECURE_BOOT
69 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
71 * HDR would be appended at end of image and copied to DDR along
74 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
75 CONFIG_U_BOOT_HDR_SIZE)
77 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
79 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
80 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
81 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
83 #define CONFIG_SPL_NAND_BOOT
86 #ifdef CONFIG_SPIFLASH
87 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
88 #define CONFIG_SPL_SPI_SUPPORT
89 #define CONFIG_SPL_SPI_FLASH_SUPPORT
90 #define CONFIG_SPL_SPI_FLASH_MINIMAL
91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
95 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
96 #ifndef CONFIG_SPL_BUILD
97 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
99 #define CONFIG_SPL_SPI_BOOT
103 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
104 #define CONFIG_SPL_MMC_SUPPORT
105 #define CONFIG_SPL_MMC_MINIMAL
106 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
107 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
108 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
109 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
110 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
111 #ifndef CONFIG_SPL_BUILD
112 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
114 #define CONFIG_SPL_MMC_BOOT
119 /* High Level Configuration Options */
121 #define CONFIG_E500MC /* BOOKE e500mc family */
122 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
123 #define CONFIG_MP /* support multiple processors */
125 /* support deep sleep */
126 #define CONFIG_DEEP_SLEEP
127 #if defined(CONFIG_DEEP_SLEEP)
128 #define CONFIG_BOARD_EARLY_INIT_F
129 #define CONFIG_SILENT_CONSOLE
132 #ifndef CONFIG_SYS_TEXT_BASE
133 #define CONFIG_SYS_TEXT_BASE 0xeff40000
136 #ifndef CONFIG_RESET_VECTOR_ADDRESS
137 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
140 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
141 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
142 #define CONFIG_FSL_IFC /* Enable IFC Support */
143 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
144 #define CONFIG_PCI /* Enable PCI/PCIE */
145 #define CONFIG_PCI_INDIRECT_BRIDGE
146 #define CONFIG_PCIE1 /* PCIE controller 1 */
147 #define CONFIG_PCIE2 /* PCIE controller 2 */
148 #define CONFIG_PCIE3 /* PCIE controller 3 */
149 #define CONFIG_PCIE4 /* PCIE controller 4 */
151 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
152 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
154 #define CONFIG_FSL_LAW /* Use common FSL init code */
156 #define CONFIG_ENV_OVERWRITE
158 #ifndef CONFIG_SYS_NO_FLASH
159 #define CONFIG_FLASH_CFI_DRIVER
160 #define CONFIG_SYS_FLASH_CFI
161 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
164 #if defined(CONFIG_SPIFLASH)
165 #define CONFIG_SYS_EXTRA_ENV_RELOC
166 #define CONFIG_ENV_IS_IN_SPI_FLASH
167 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
168 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
169 #define CONFIG_ENV_SECT_SIZE 0x10000
170 #elif defined(CONFIG_SDCARD)
171 #define CONFIG_SYS_EXTRA_ENV_RELOC
172 #define CONFIG_ENV_IS_IN_MMC
173 #define CONFIG_SYS_MMC_ENV_DEV 0
174 #define CONFIG_ENV_SIZE 0x2000
175 #define CONFIG_ENV_OFFSET (512 * 0x800)
176 #elif defined(CONFIG_NAND)
177 #ifdef CONFIG_SECURE_BOOT
178 #define CONFIG_RAMBOOT_NAND
179 #define CONFIG_BOOTSCRIPT_COPY_RAM
181 #define CONFIG_SYS_EXTRA_ENV_RELOC
182 #define CONFIG_ENV_IS_IN_NAND
183 #define CONFIG_ENV_SIZE 0x2000
184 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
186 #define CONFIG_ENV_IS_IN_FLASH
187 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
188 #define CONFIG_ENV_SIZE 0x2000
189 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
192 #define CONFIG_SYS_CLK_FREQ 100000000
193 #define CONFIG_DDR_CLK_FREQ 66666666
196 * These can be toggled for performance analysis, otherwise use default.
198 #define CONFIG_SYS_CACHE_STASHING
199 #define CONFIG_BACKSIDE_L2_CACHE
200 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
201 #define CONFIG_BTB /* toggle branch predition */
202 #define CONFIG_DDR_ECC
203 #ifdef CONFIG_DDR_ECC
204 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
205 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
208 #define CONFIG_ENABLE_36BIT_PHYS
210 #define CONFIG_ADDR_MAP
211 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
213 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
214 #define CONFIG_SYS_MEMTEST_END 0x00400000
215 #define CONFIG_SYS_ALT_MEMTEST
216 #define CONFIG_PANIC_HANG /* do not reset board on panic */
219 * Config the L3 Cache as L3 SRAM
221 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
223 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
224 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
225 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
227 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
228 #define CONFIG_SYS_L3_SIZE 256 << 10
229 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
230 #ifdef CONFIG_RAMBOOT_PBL
231 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
233 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
234 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
235 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
236 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
238 #define CONFIG_SYS_DCSRBAR 0xf0000000
239 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
244 #define CONFIG_VERY_BIG_RAM
245 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
246 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
248 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
249 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
250 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
252 #define CONFIG_DDR_SPD
253 #ifndef CONFIG_SYS_FSL_DDR4
254 #define CONFIG_SYS_FSL_DDR3
257 #define CONFIG_SYS_SPD_BUS_NUM 0
258 #define SPD_EEPROM_ADDRESS 0x51
260 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
265 #define CONFIG_SYS_FLASH_BASE 0xe8000000
266 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
268 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
269 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
270 CSPR_PORT_SIZE_16 | \
273 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
278 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
280 /* NOR Flash Timing Params */
281 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
282 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
283 FTIM0_NOR_TEADC(0x5) | \
284 FTIM0_NOR_TEAHC(0x5))
285 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
286 FTIM1_NOR_TRAD_NOR(0x1A) |\
287 FTIM1_NOR_TSEQRAD_NOR(0x13))
288 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
289 FTIM2_NOR_TCH(0x4) | \
290 FTIM2_NOR_TWPH(0x0E) | \
292 #define CONFIG_SYS_NOR_FTIM3 0x0
294 #define CONFIG_SYS_FLASH_QUIET_TEST
295 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
297 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
298 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
299 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
300 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
302 #define CONFIG_SYS_FLASH_EMPTY_INFO
303 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
306 #define CPLD_LBMAP_MASK 0x3F
307 #define CPLD_BANK_SEL_MASK 0x07
308 #define CPLD_BANK_OVERRIDE 0x40
309 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
310 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
311 #define CPLD_LBMAP_RESET 0xFF
312 #define CPLD_LBMAP_SHIFT 0x03
314 #if defined(CONFIG_T1042RDB_PI)
315 #define CPLD_DIU_SEL_DFP 0x80
316 #elif defined(CONFIG_T1042D4RDB)
317 #define CPLD_DIU_SEL_DFP 0xc0
320 #if defined(CONFIG_T1040D4RDB)
321 #define CPLD_INT_MASK_ALL 0xFF
322 #define CPLD_INT_MASK_THERM 0x80
323 #define CPLD_INT_MASK_DVI_DFP 0x40
324 #define CPLD_INT_MASK_QSGMII1 0x20
325 #define CPLD_INT_MASK_QSGMII2 0x10
326 #define CPLD_INT_MASK_SGMI1 0x08
327 #define CPLD_INT_MASK_SGMI2 0x04
328 #define CPLD_INT_MASK_TDMR1 0x02
329 #define CPLD_INT_MASK_TDMR2 0x01
332 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
333 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
334 #define CONFIG_SYS_CSPR2_EXT (0xf)
335 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
339 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
340 #define CONFIG_SYS_CSOR2 0x0
341 /* CPLD Timing parameters for IFC CS2 */
342 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
343 FTIM0_GPCM_TEADC(0x0e) | \
344 FTIM0_GPCM_TEAHC(0x0e))
345 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
346 FTIM1_GPCM_TRAD(0x1f))
347 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
348 FTIM2_GPCM_TCH(0x8) | \
349 FTIM2_GPCM_TWP(0x1f))
350 #define CONFIG_SYS_CS2_FTIM3 0x0
352 /* NAND Flash on IFC */
353 #define CONFIG_NAND_FSL_IFC
354 #define CONFIG_SYS_NAND_BASE 0xff800000
355 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
357 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
358 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
359 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
360 | CSPR_MSEL_NAND /* MSEL = NAND */ \
362 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
364 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
365 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
366 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
367 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
368 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
369 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
370 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
372 #define CONFIG_SYS_NAND_ONFI_DETECTION
374 /* ONFI NAND Flash mode0 Timing Params */
375 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
376 FTIM0_NAND_TWP(0x18) | \
377 FTIM0_NAND_TWCHT(0x07) | \
378 FTIM0_NAND_TWH(0x0a))
379 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
380 FTIM1_NAND_TWBE(0x39) | \
381 FTIM1_NAND_TRR(0x0e) | \
382 FTIM1_NAND_TRP(0x18))
383 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
384 FTIM2_NAND_TREH(0x0a) | \
385 FTIM2_NAND_TWHRE(0x1e))
386 #define CONFIG_SYS_NAND_FTIM3 0x0
388 #define CONFIG_SYS_NAND_DDR_LAW 11
389 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
390 #define CONFIG_SYS_MAX_NAND_DEVICE 1
391 #define CONFIG_CMD_NAND
393 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
395 #if defined(CONFIG_NAND)
396 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
397 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
398 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
399 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
400 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
401 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
402 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
403 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
404 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
405 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
406 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
407 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
408 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
409 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
410 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
411 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
413 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
414 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
415 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
416 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
417 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
418 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
419 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
420 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
421 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
422 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
423 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
424 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
425 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
426 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
427 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
428 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
431 #ifdef CONFIG_SPL_BUILD
432 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
434 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
437 #if defined(CONFIG_RAMBOOT_PBL)
438 #define CONFIG_SYS_RAMBOOT
441 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
442 #if defined(CONFIG_NAND)
443 #define CONFIG_A008044_WORKAROUND
447 #define CONFIG_BOARD_EARLY_INIT_R
448 #define CONFIG_MISC_INIT_R
450 #define CONFIG_HWCONFIG
452 /* define to use L1 as initial stack */
453 #define CONFIG_L1_INIT_RAM
454 #define CONFIG_SYS_INIT_RAM_LOCK
455 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
458 /* The assembler doesn't like typecast */
459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
460 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
461 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
462 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
464 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
465 GENERATED_GBL_DATA_SIZE)
466 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
468 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
469 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
471 /* Serial Port - controlled on board with jumper J8
475 #define CONFIG_CONS_INDEX 1
476 #define CONFIG_SYS_NS16550_SERIAL
477 #define CONFIG_SYS_NS16550_REG_SIZE 1
478 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
480 #define CONFIG_SYS_BAUDRATE_TABLE \
481 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
483 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
484 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
485 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
486 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
487 #ifndef CONFIG_SPL_BUILD
488 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
491 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
493 #define CONFIG_FSL_DIU_FB
495 #ifdef CONFIG_FSL_DIU_FB
496 #define CONFIG_FSL_DIU_CH7301
497 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
499 #define CONFIG_CMD_BMP
500 #define CONFIG_CFB_CONSOLE
501 #define CONFIG_CFB_CONSOLE_ANSI
502 #define CONFIG_VIDEO_SW_CURSOR
503 #define CONFIG_VGA_AS_SINGLE_DEVICE
504 #define CONFIG_VIDEO_LOGO
505 #define CONFIG_VIDEO_BMP_LOGO
510 #define CONFIG_SYS_I2C
511 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
512 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
513 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
514 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
515 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
516 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
517 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
518 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
519 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
520 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
521 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
522 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
523 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
525 /* I2C bus multiplexer */
526 #define I2C_MUX_PCA_ADDR 0x70
527 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
528 #define I2C_MUX_CH_DEFAULT 0x8
531 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
532 /* LDI/DVI Encoder for display */
533 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
534 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
540 #define CONFIG_RTC_DS1337 1
541 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
544 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
548 * eSPI - Enhanced SPI
550 #define CONFIG_SPI_FLASH_BAR
551 #define CONFIG_SF_DEFAULT_SPEED 10000000
552 #define CONFIG_SF_DEFAULT_MODE 0
553 #define CONFIG_ENV_SPI_BUS 0
554 #define CONFIG_ENV_SPI_CS 0
555 #define CONFIG_ENV_SPI_MAX_HZ 10000000
556 #define CONFIG_ENV_SPI_MODE 0
560 * Memory space is mapped 1-1, but I/O space must start from 0.
564 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
566 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
567 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
568 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
569 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
570 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
571 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
572 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
573 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
576 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
578 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
579 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
580 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
581 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
582 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
583 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
584 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
585 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
588 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
590 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
591 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
592 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
593 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
594 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
595 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
596 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
597 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
600 /* controller 4, Base address 203000 */
602 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
603 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
604 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
605 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
606 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
607 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
608 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
609 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
612 #define CONFIG_PCI_PNP /* do pci plug-and-play */
614 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
615 #define CONFIG_DOS_PARTITION
616 #endif /* CONFIG_PCI */
619 #define CONFIG_FSL_SATA_V2
620 #ifdef CONFIG_FSL_SATA_V2
621 #define CONFIG_LIBATA
622 #define CONFIG_FSL_SATA
624 #define CONFIG_SYS_SATA_MAX_DEVICE 1
626 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
627 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
630 #define CONFIG_CMD_SATA
631 #define CONFIG_DOS_PARTITION
637 #define CONFIG_HAS_FSL_DR_USB
639 #ifdef CONFIG_HAS_FSL_DR_USB
640 #define CONFIG_USB_EHCI
642 #ifdef CONFIG_USB_EHCI
643 #define CONFIG_USB_EHCI_FSL
644 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
651 #define CONFIG_FSL_ESDHC
652 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
653 #define CONFIG_GENERIC_MMC
654 #define CONFIG_DOS_PARTITION
658 #ifndef CONFIG_NOBQFMAN
659 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
660 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
661 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
662 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
663 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
664 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
665 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
666 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
667 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
668 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
669 CONFIG_SYS_BMAN_CENA_SIZE)
670 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
671 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
672 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
673 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
674 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
675 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
676 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
677 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
678 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
679 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
680 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
681 CONFIG_SYS_QMAN_CENA_SIZE)
682 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
683 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
685 #define CONFIG_SYS_DPAA_FMAN
686 #define CONFIG_SYS_DPAA_PME
688 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
693 /* Default address of microcode for the Linux Fman driver */
694 #if defined(CONFIG_SPIFLASH)
696 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
697 * env, so we got 0x110000.
699 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
700 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
701 #elif defined(CONFIG_SDCARD)
703 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
704 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
705 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
707 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
708 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
709 #elif defined(CONFIG_NAND)
710 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
711 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
713 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
714 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
717 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
718 #if defined(CONFIG_SPIFLASH)
719 #define CONFIG_SYS_QE_FW_ADDR 0x130000
720 #elif defined(CONFIG_SDCARD)
721 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
722 #elif defined(CONFIG_NAND)
723 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
725 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
729 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
730 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
731 #endif /* CONFIG_NOBQFMAN */
733 #ifdef CONFIG_SYS_DPAA_FMAN
734 #define CONFIG_FMAN_ENET
735 #define CONFIG_PHY_VITESSE
736 #define CONFIG_PHY_REALTEK
739 #ifdef CONFIG_FMAN_ENET
740 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
741 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
742 #elif defined(CONFIG_T1040D4RDB)
743 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
744 #elif defined(CONFIG_T1042D4RDB)
745 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
746 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
747 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
750 #ifdef CONFIG_T104XD4RDB
751 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
752 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
754 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
755 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
758 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
759 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
760 #define CONFIG_VSC9953
761 #define CONFIG_CMD_ETHSW
762 #ifdef CONFIG_T1040RDB
763 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
764 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
766 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
767 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
771 #define CONFIG_MII /* MII PHY management */
772 #define CONFIG_ETHPRIME "FM1@DTSEC4"
773 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
779 #define CONFIG_LOADS_ECHO /* echo on for serial download */
780 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
783 * Command line configuration.
785 #ifdef CONFIG_T1042RDB_PI
786 #define CONFIG_CMD_DATE
788 #define CONFIG_CMD_ERRATA
789 #define CONFIG_CMD_IRQ
790 #define CONFIG_CMD_REGINFO
793 #define CONFIG_CMD_PCI
796 /* Hash command with SHA acceleration supported in hardware */
797 #ifdef CONFIG_FSL_CAAM
798 #define CONFIG_CMD_HASH
799 #define CONFIG_SHA_HW_ACCEL
803 * Miscellaneous configurable options
805 #define CONFIG_SYS_LONGHELP /* undef to save memory */
806 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
807 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
808 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
809 #ifdef CONFIG_CMD_KGDB
810 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
812 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
814 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
815 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
816 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
819 * For booting Linux, the board info and command line data
820 * have to be in the first 64 MB of memory, since this is
821 * the maximum mapped by the Linux kernel during initialization.
823 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
824 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
826 #ifdef CONFIG_CMD_KGDB
827 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
831 * Dynamic MTD Partition support with mtdparts
833 #ifndef CONFIG_SYS_NO_FLASH
834 #define CONFIG_MTD_DEVICE
835 #define CONFIG_MTD_PARTITIONS
836 #define CONFIG_CMD_MTDPARTS
837 #define CONFIG_FLASH_CFI_MTD
838 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
840 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
841 "128k(dtb),96m(fs),-(user);"\
842 "fff800000.flash:2m(uboot),9m(kernel),"\
843 "128k(dtb),96m(fs),-(user);spife110000.0:" \
844 "2m(uboot),9m(kernel),128k(dtb),-(user)"
848 * Environment Configuration
850 #define CONFIG_ROOTPATH "/opt/nfsroot"
851 #define CONFIG_BOOTFILE "uImage"
852 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
854 /* default location for tftp and bootm */
855 #define CONFIG_LOADADDR 1000000
858 #define CONFIG_BAUDRATE 115200
860 #define __USB_PHY_TYPE utmi
861 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
863 #ifdef CONFIG_T1040RDB
864 #define FDTFILE "t1040rdb/t1040rdb.dtb"
865 #elif defined(CONFIG_T1042RDB_PI)
866 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
867 #elif defined(CONFIG_T1042RDB)
868 #define FDTFILE "t1042rdb/t1042rdb.dtb"
869 #elif defined(CONFIG_T1040D4RDB)
870 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
871 #elif defined(CONFIG_T1042D4RDB)
872 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
875 #ifdef CONFIG_FSL_DIU_FB
876 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
878 #define DIU_ENVIRONMENT
881 #define CONFIG_EXTRA_ENV_SETTINGS \
882 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
883 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
884 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
886 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
887 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
888 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
889 "tftpflash=tftpboot $loadaddr $uboot && " \
890 "protect off $ubootaddr +$filesize && " \
891 "erase $ubootaddr +$filesize && " \
892 "cp.b $loadaddr $ubootaddr $filesize && " \
893 "protect on $ubootaddr +$filesize && " \
894 "cmp.b $loadaddr $ubootaddr $filesize\0" \
895 "consoledev=ttyS0\0" \
896 "ramdiskaddr=2000000\0" \
897 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
898 "fdtaddr=1e00000\0" \
899 "fdtfile=" __stringify(FDTFILE) "\0" \
902 #define CONFIG_LINUX \
903 "setenv bootargs root=/dev/ram rw " \
904 "console=$consoledev,$baudrate $othbootargs;" \
905 "setenv ramdiskaddr 0x02000000;" \
906 "setenv fdtaddr 0x00c00000;" \
907 "setenv loadaddr 0x1000000;" \
908 "bootm $loadaddr $ramdiskaddr $fdtaddr"
910 #define CONFIG_HDBOOT \
911 "setenv bootargs root=/dev/$bdev rw " \
912 "console=$consoledev,$baudrate $othbootargs;" \
913 "tftp $loadaddr $bootfile;" \
914 "tftp $fdtaddr $fdtfile;" \
915 "bootm $loadaddr - $fdtaddr"
917 #define CONFIG_NFSBOOTCOMMAND \
918 "setenv bootargs root=/dev/nfs rw " \
919 "nfsroot=$serverip:$rootpath " \
920 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
921 "console=$consoledev,$baudrate $othbootargs;" \
922 "tftp $loadaddr $bootfile;" \
923 "tftp $fdtaddr $fdtfile;" \
924 "bootm $loadaddr - $fdtaddr"
926 #define CONFIG_RAMBOOTCOMMAND \
927 "setenv bootargs root=/dev/ram rw " \
928 "console=$consoledev,$baudrate $othbootargs;" \
929 "tftp $ramdiskaddr $ramdiskfile;" \
930 "tftp $loadaddr $bootfile;" \
931 "tftp $fdtaddr $fdtfile;" \
932 "bootm $loadaddr $ramdiskaddr $fdtaddr"
934 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
936 #include <asm/fsl_secure_boot.h>
938 #endif /* __CONFIG_H */