2 + * Copyright 2014 Freescale Semiconductor, Inc.
4 + * SPDX-License-Identifier: GPL-2.0+
11 * T104x RDB board configuration file
13 #include <asm/config_mpc85xx.h>
15 #ifdef CONFIG_RAMBOOT_PBL
17 #ifndef CONFIG_SECURE_BOOT
18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
20 #define CONFIG_SYS_FSL_PBL_PBI \
21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26 #define CONFIG_SYS_TEXT_BASE 0x30001000
27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
28 #define CONFIG_SPL_PAD_TO 0x40000
29 #define CONFIG_SPL_MAX_SIZE 0x28000
30 #ifdef CONFIG_SPL_BUILD
31 #define CONFIG_SPL_SKIP_RELOCATE
32 #define CONFIG_SPL_COMMON_INIT_DDR
33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
35 #define RESET_VECTOR_OFFSET 0x27FFC
36 #define BOOT_PAGE_OFFSET 0x27000
39 #ifdef CONFIG_SECURE_BOOT
40 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
42 * HDR would be appended at end of image and copied to DDR along
45 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
46 CONFIG_U_BOOT_HDR_SIZE)
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
51 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
52 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
54 #ifdef CONFIG_TARGET_T1040RDB
55 #define CONFIG_SYS_FSL_PBL_RCW \
56 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
58 #ifdef CONFIG_TARGET_T1042RDB_PI
59 #define CONFIG_SYS_FSL_PBL_RCW \
60 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
62 #ifdef CONFIG_TARGET_T1042RDB
63 #define CONFIG_SYS_FSL_PBL_RCW \
64 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
66 #ifdef CONFIG_TARGET_T1040D4RDB
67 #define CONFIG_SYS_FSL_PBL_RCW \
68 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
70 #ifdef CONFIG_TARGET_T1042D4RDB
71 #define CONFIG_SYS_FSL_PBL_RCW \
72 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
74 #define CONFIG_SPL_NAND_BOOT
77 #ifdef CONFIG_SPIFLASH
78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
79 #define CONFIG_SPL_SPI_FLASH_MINIMAL
80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
85 #ifndef CONFIG_SPL_BUILD
86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
88 #ifdef CONFIG_TARGET_T1040RDB
89 #define CONFIG_SYS_FSL_PBL_RCW \
90 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
92 #ifdef CONFIG_TARGET_T1042RDB_PI
93 #define CONFIG_SYS_FSL_PBL_RCW \
94 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
96 #ifdef CONFIG_TARGET_T1042RDB
97 #define CONFIG_SYS_FSL_PBL_RCW \
98 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
100 #ifdef CONFIG_TARGET_T1040D4RDB
101 #define CONFIG_SYS_FSL_PBL_RCW \
102 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
104 #ifdef CONFIG_TARGET_T1042D4RDB
105 #define CONFIG_SYS_FSL_PBL_RCW \
106 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
108 #define CONFIG_SPL_SPI_BOOT
112 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
113 #define CONFIG_SPL_MMC_MINIMAL
114 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
115 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
116 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
117 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
118 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
119 #ifndef CONFIG_SPL_BUILD
120 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
122 #ifdef CONFIG_TARGET_T1040RDB
123 #define CONFIG_SYS_FSL_PBL_RCW \
124 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
126 #ifdef CONFIG_TARGET_T1042RDB_PI
127 #define CONFIG_SYS_FSL_PBL_RCW \
128 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
130 #ifdef CONFIG_TARGET_T1042RDB
131 #define CONFIG_SYS_FSL_PBL_RCW \
132 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
134 #ifdef CONFIG_TARGET_T1040D4RDB
135 #define CONFIG_SYS_FSL_PBL_RCW \
136 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
138 #ifdef CONFIG_TARGET_T1042D4RDB
139 #define CONFIG_SYS_FSL_PBL_RCW \
140 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
142 #define CONFIG_SPL_MMC_BOOT
147 /* High Level Configuration Options */
148 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
149 #define CONFIG_MP /* support multiple processors */
151 /* support deep sleep */
152 #define CONFIG_DEEP_SLEEP
154 #ifndef CONFIG_SYS_TEXT_BASE
155 #define CONFIG_SYS_TEXT_BASE 0xeff40000
158 #ifndef CONFIG_RESET_VECTOR_ADDRESS
159 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
162 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
163 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
164 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
165 #define CONFIG_PCI_INDIRECT_BRIDGE
166 #define CONFIG_PCIE1 /* PCIE controller 1 */
167 #define CONFIG_PCIE2 /* PCIE controller 2 */
168 #define CONFIG_PCIE3 /* PCIE controller 3 */
169 #define CONFIG_PCIE4 /* PCIE controller 4 */
171 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
172 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
174 #define CONFIG_ENV_OVERWRITE
176 #ifdef CONFIG_MTD_NOR_FLASH
177 #define CONFIG_FLASH_CFI_DRIVER
178 #define CONFIG_SYS_FLASH_CFI
179 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
182 #if defined(CONFIG_SPIFLASH)
183 #define CONFIG_SYS_EXTRA_ENV_RELOC
184 #define CONFIG_ENV_IS_IN_SPI_FLASH
185 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
186 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
187 #define CONFIG_ENV_SECT_SIZE 0x10000
188 #elif defined(CONFIG_SDCARD)
189 #define CONFIG_SYS_EXTRA_ENV_RELOC
190 #define CONFIG_ENV_IS_IN_MMC
191 #define CONFIG_SYS_MMC_ENV_DEV 0
192 #define CONFIG_ENV_SIZE 0x2000
193 #define CONFIG_ENV_OFFSET (512 * 0x800)
194 #elif defined(CONFIG_NAND)
195 #ifdef CONFIG_SECURE_BOOT
196 #define CONFIG_RAMBOOT_NAND
197 #define CONFIG_BOOTSCRIPT_COPY_RAM
199 #define CONFIG_SYS_EXTRA_ENV_RELOC
200 #define CONFIG_ENV_IS_IN_NAND
201 #define CONFIG_ENV_SIZE 0x2000
202 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
204 #define CONFIG_ENV_IS_IN_FLASH
205 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
206 #define CONFIG_ENV_SIZE 0x2000
207 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
210 #define CONFIG_SYS_CLK_FREQ 100000000
211 #define CONFIG_DDR_CLK_FREQ 66666666
214 * These can be toggled for performance analysis, otherwise use default.
216 #define CONFIG_SYS_CACHE_STASHING
217 #define CONFIG_BACKSIDE_L2_CACHE
218 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
219 #define CONFIG_BTB /* toggle branch predition */
220 #define CONFIG_DDR_ECC
221 #ifdef CONFIG_DDR_ECC
222 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
223 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
226 #define CONFIG_ENABLE_36BIT_PHYS
228 #define CONFIG_ADDR_MAP
229 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
231 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
232 #define CONFIG_SYS_MEMTEST_END 0x00400000
233 #define CONFIG_SYS_ALT_MEMTEST
234 #define CONFIG_PANIC_HANG /* do not reset board on panic */
237 * Config the L3 Cache as L3 SRAM
239 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
241 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
242 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
243 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
245 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
246 #define CONFIG_SYS_L3_SIZE 256 << 10
247 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
248 #ifdef CONFIG_RAMBOOT_PBL
249 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
251 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
252 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
253 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
254 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
256 #define CONFIG_SYS_DCSRBAR 0xf0000000
257 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
262 #define CONFIG_VERY_BIG_RAM
263 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
264 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
266 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
267 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
269 #define CONFIG_DDR_SPD
271 #define CONFIG_SYS_SPD_BUS_NUM 0
272 #define SPD_EEPROM_ADDRESS 0x51
274 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
279 #define CONFIG_SYS_FLASH_BASE 0xe8000000
280 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
282 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
283 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
284 CSPR_PORT_SIZE_16 | \
287 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
292 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
294 /* NOR Flash Timing Params */
295 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
296 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
297 FTIM0_NOR_TEADC(0x5) | \
298 FTIM0_NOR_TEAHC(0x5))
299 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
300 FTIM1_NOR_TRAD_NOR(0x1A) |\
301 FTIM1_NOR_TSEQRAD_NOR(0x13))
302 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
303 FTIM2_NOR_TCH(0x4) | \
304 FTIM2_NOR_TWPH(0x0E) | \
306 #define CONFIG_SYS_NOR_FTIM3 0x0
308 #define CONFIG_SYS_FLASH_QUIET_TEST
309 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
311 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
312 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
313 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
314 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
316 #define CONFIG_SYS_FLASH_EMPTY_INFO
317 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
320 #define CPLD_LBMAP_MASK 0x3F
321 #define CPLD_BANK_SEL_MASK 0x07
322 #define CPLD_BANK_OVERRIDE 0x40
323 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
324 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
325 #define CPLD_LBMAP_RESET 0xFF
326 #define CPLD_LBMAP_SHIFT 0x03
328 #if defined(CONFIG_TARGET_T1042RDB_PI)
329 #define CPLD_DIU_SEL_DFP 0x80
330 #elif defined(CONFIG_TARGET_T1042D4RDB)
331 #define CPLD_DIU_SEL_DFP 0xc0
334 #if defined(CONFIG_TARGET_T1040D4RDB)
335 #define CPLD_INT_MASK_ALL 0xFF
336 #define CPLD_INT_MASK_THERM 0x80
337 #define CPLD_INT_MASK_DVI_DFP 0x40
338 #define CPLD_INT_MASK_QSGMII1 0x20
339 #define CPLD_INT_MASK_QSGMII2 0x10
340 #define CPLD_INT_MASK_SGMI1 0x08
341 #define CPLD_INT_MASK_SGMI2 0x04
342 #define CPLD_INT_MASK_TDMR1 0x02
343 #define CPLD_INT_MASK_TDMR2 0x01
346 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
347 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
348 #define CONFIG_SYS_CSPR2_EXT (0xf)
349 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
353 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
354 #define CONFIG_SYS_CSOR2 0x0
355 /* CPLD Timing parameters for IFC CS2 */
356 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
357 FTIM0_GPCM_TEADC(0x0e) | \
358 FTIM0_GPCM_TEAHC(0x0e))
359 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
360 FTIM1_GPCM_TRAD(0x1f))
361 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
362 FTIM2_GPCM_TCH(0x8) | \
363 FTIM2_GPCM_TWP(0x1f))
364 #define CONFIG_SYS_CS2_FTIM3 0x0
366 /* NAND Flash on IFC */
367 #define CONFIG_NAND_FSL_IFC
368 #define CONFIG_SYS_NAND_BASE 0xff800000
369 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
371 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
372 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
373 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
374 | CSPR_MSEL_NAND /* MSEL = NAND */ \
376 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
378 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
379 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
380 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
381 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
382 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
383 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
384 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
386 #define CONFIG_SYS_NAND_ONFI_DETECTION
388 /* ONFI NAND Flash mode0 Timing Params */
389 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
390 FTIM0_NAND_TWP(0x18) | \
391 FTIM0_NAND_TWCHT(0x07) | \
392 FTIM0_NAND_TWH(0x0a))
393 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
394 FTIM1_NAND_TWBE(0x39) | \
395 FTIM1_NAND_TRR(0x0e) | \
396 FTIM1_NAND_TRP(0x18))
397 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
398 FTIM2_NAND_TREH(0x0a) | \
399 FTIM2_NAND_TWHRE(0x1e))
400 #define CONFIG_SYS_NAND_FTIM3 0x0
402 #define CONFIG_SYS_NAND_DDR_LAW 11
403 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
404 #define CONFIG_SYS_MAX_NAND_DEVICE 1
405 #define CONFIG_CMD_NAND
407 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
409 #if defined(CONFIG_NAND)
410 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
411 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
412 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
413 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
414 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
415 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
416 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
417 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
418 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
419 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
420 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
421 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
422 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
423 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
424 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
425 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
427 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
428 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
429 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
430 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
431 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
432 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
433 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
434 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
435 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
436 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
437 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
438 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
439 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
440 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
441 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
442 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
445 #ifdef CONFIG_SPL_BUILD
446 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
448 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
451 #if defined(CONFIG_RAMBOOT_PBL)
452 #define CONFIG_SYS_RAMBOOT
455 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
456 #if defined(CONFIG_NAND)
457 #define CONFIG_A008044_WORKAROUND
461 #define CONFIG_BOARD_EARLY_INIT_R
462 #define CONFIG_MISC_INIT_R
464 #define CONFIG_HWCONFIG
466 /* define to use L1 as initial stack */
467 #define CONFIG_L1_INIT_RAM
468 #define CONFIG_SYS_INIT_RAM_LOCK
469 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
472 /* The assembler doesn't like typecast */
473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
474 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
475 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
476 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
478 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
479 GENERATED_GBL_DATA_SIZE)
480 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
482 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
483 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
485 /* Serial Port - controlled on board with jumper J8
489 #define CONFIG_CONS_INDEX 1
490 #define CONFIG_SYS_NS16550_SERIAL
491 #define CONFIG_SYS_NS16550_REG_SIZE 1
492 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
494 #define CONFIG_SYS_BAUDRATE_TABLE \
495 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
497 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
498 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
499 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
500 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
502 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
504 #define CONFIG_FSL_DIU_FB
506 #ifdef CONFIG_FSL_DIU_FB
507 #define CONFIG_FSL_DIU_CH7301
508 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
509 #define CONFIG_CMD_BMP
510 #define CONFIG_VIDEO_LOGO
511 #define CONFIG_VIDEO_BMP_LOGO
516 #define CONFIG_SYS_I2C
517 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
518 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
519 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
520 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
521 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
522 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
523 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
524 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
525 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
526 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
527 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
528 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
529 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
531 /* I2C bus multiplexer */
532 #define I2C_MUX_PCA_ADDR 0x70
533 #define I2C_MUX_CH_DEFAULT 0x8
535 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
536 defined(CONFIG_TARGET_T1040D4RDB) || \
537 defined(CONFIG_TARGET_T1042D4RDB)
538 /* LDI/DVI Encoder for display */
539 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
540 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
546 #define CONFIG_RTC_DS1337 1
547 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
550 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
554 * eSPI - Enhanced SPI
556 #define CONFIG_SPI_FLASH_BAR
557 #define CONFIG_SF_DEFAULT_SPEED 10000000
558 #define CONFIG_SF_DEFAULT_MODE 0
559 #define CONFIG_ENV_SPI_BUS 0
560 #define CONFIG_ENV_SPI_CS 0
561 #define CONFIG_ENV_SPI_MAX_HZ 10000000
562 #define CONFIG_ENV_SPI_MODE 0
566 * Memory space is mapped 1-1, but I/O space must start from 0.
570 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
572 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
573 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
574 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
575 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
576 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
577 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
578 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
579 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
582 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
584 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
585 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
586 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
587 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
588 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
589 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
590 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
591 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
594 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
596 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
597 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
598 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
599 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
600 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
601 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
602 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
603 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
606 /* controller 4, Base address 203000 */
608 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
609 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
610 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
611 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
612 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
613 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
614 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
615 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
618 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
619 #endif /* CONFIG_PCI */
622 #define CONFIG_FSL_SATA_V2
623 #ifdef CONFIG_FSL_SATA_V2
624 #define CONFIG_LIBATA
625 #define CONFIG_FSL_SATA
627 #define CONFIG_SYS_SATA_MAX_DEVICE 1
629 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
630 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
633 #define CONFIG_CMD_SATA
639 #define CONFIG_HAS_FSL_DR_USB
641 #ifdef CONFIG_HAS_FSL_DR_USB
642 #define CONFIG_USB_EHCI
644 #ifdef CONFIG_USB_EHCI
645 #define CONFIG_USB_EHCI_FSL
646 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
651 #define CONFIG_FSL_ESDHC
652 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
656 #ifndef CONFIG_NOBQFMAN
657 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
658 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
659 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
660 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
661 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
662 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
663 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
664 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
665 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
666 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
667 CONFIG_SYS_BMAN_CENA_SIZE)
668 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
669 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
670 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
671 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
672 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
673 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
674 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
675 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
676 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
677 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
678 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
679 CONFIG_SYS_QMAN_CENA_SIZE)
680 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
681 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
683 #define CONFIG_SYS_DPAA_FMAN
684 #define CONFIG_SYS_DPAA_PME
689 /* Default address of microcode for the Linux Fman driver */
690 #if defined(CONFIG_SPIFLASH)
692 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
693 * env, so we got 0x110000.
695 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
696 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
697 #elif defined(CONFIG_SDCARD)
699 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
700 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
701 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
703 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
704 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
705 #elif defined(CONFIG_NAND)
706 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
707 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
709 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
710 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
713 #if defined(CONFIG_SPIFLASH)
714 #define CONFIG_SYS_QE_FW_ADDR 0x130000
715 #elif defined(CONFIG_SDCARD)
716 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
717 #elif defined(CONFIG_NAND)
718 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
720 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
723 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
724 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
725 #endif /* CONFIG_NOBQFMAN */
727 #ifdef CONFIG_SYS_DPAA_FMAN
728 #define CONFIG_FMAN_ENET
729 #define CONFIG_PHY_VITESSE
730 #define CONFIG_PHY_REALTEK
733 #ifdef CONFIG_FMAN_ENET
734 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
735 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
736 #elif defined(CONFIG_TARGET_T1040D4RDB)
737 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
738 #elif defined(CONFIG_TARGET_T1042D4RDB)
739 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
740 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
741 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
744 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
745 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
746 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
748 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
749 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
752 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
753 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
754 #define CONFIG_VSC9953
755 #define CONFIG_CMD_ETHSW
756 #ifdef CONFIG_TARGET_T1040RDB
757 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
758 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
760 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
761 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
765 #define CONFIG_MII /* MII PHY management */
766 #define CONFIG_ETHPRIME "FM1@DTSEC4"
767 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
773 #define CONFIG_LOADS_ECHO /* echo on for serial download */
774 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
777 * Command line configuration.
779 #ifdef CONFIG_TARGET_T1042RDB_PI
780 #define CONFIG_CMD_DATE
782 #define CONFIG_CMD_ERRATA
783 #define CONFIG_CMD_IRQ
784 #define CONFIG_CMD_REGINFO
787 #define CONFIG_CMD_PCI
790 /* Hash command with SHA acceleration supported in hardware */
791 #ifdef CONFIG_FSL_CAAM
792 #define CONFIG_CMD_HASH
793 #define CONFIG_SHA_HW_ACCEL
797 * Miscellaneous configurable options
799 #define CONFIG_SYS_LONGHELP /* undef to save memory */
800 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
801 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
802 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
803 #ifdef CONFIG_CMD_KGDB
804 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
806 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
808 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
809 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
810 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
813 * For booting Linux, the board info and command line data
814 * have to be in the first 64 MB of memory, since this is
815 * the maximum mapped by the Linux kernel during initialization.
817 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
818 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
820 #ifdef CONFIG_CMD_KGDB
821 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
825 * Dynamic MTD Partition support with mtdparts
827 #ifdef CONFIG_MTD_NOR_FLASH
828 #define CONFIG_MTD_DEVICE
829 #define CONFIG_MTD_PARTITIONS
830 #define CONFIG_CMD_MTDPARTS
831 #define CONFIG_FLASH_CFI_MTD
832 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
834 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
835 "128k(dtb),96m(fs),-(user);"\
836 "fff800000.flash:2m(uboot),9m(kernel),"\
837 "128k(dtb),96m(fs),-(user);spife110000.0:" \
838 "2m(uboot),9m(kernel),128k(dtb),-(user)"
842 * Environment Configuration
844 #define CONFIG_ROOTPATH "/opt/nfsroot"
845 #define CONFIG_BOOTFILE "uImage"
846 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
848 /* default location for tftp and bootm */
849 #define CONFIG_LOADADDR 1000000
852 #define CONFIG_BAUDRATE 115200
854 #define __USB_PHY_TYPE utmi
855 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
857 #ifdef CONFIG_TARGET_T1040RDB
858 #define FDTFILE "t1040rdb/t1040rdb.dtb"
859 #elif defined(CONFIG_TARGET_T1042RDB_PI)
860 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
861 #elif defined(CONFIG_TARGET_T1042RDB)
862 #define FDTFILE "t1042rdb/t1042rdb.dtb"
863 #elif defined(CONFIG_TARGET_T1040D4RDB)
864 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
865 #elif defined(CONFIG_TARGET_T1042D4RDB)
866 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
869 #ifdef CONFIG_FSL_DIU_FB
870 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
872 #define DIU_ENVIRONMENT
875 #define CONFIG_EXTRA_ENV_SETTINGS \
876 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
877 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
878 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
880 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
881 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
882 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
883 "tftpflash=tftpboot $loadaddr $uboot && " \
884 "protect off $ubootaddr +$filesize && " \
885 "erase $ubootaddr +$filesize && " \
886 "cp.b $loadaddr $ubootaddr $filesize && " \
887 "protect on $ubootaddr +$filesize && " \
888 "cmp.b $loadaddr $ubootaddr $filesize\0" \
889 "consoledev=ttyS0\0" \
890 "ramdiskaddr=2000000\0" \
891 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
892 "fdtaddr=1e00000\0" \
893 "fdtfile=" __stringify(FDTFILE) "\0" \
896 #define CONFIG_LINUX \
897 "setenv bootargs root=/dev/ram rw " \
898 "console=$consoledev,$baudrate $othbootargs;" \
899 "setenv ramdiskaddr 0x02000000;" \
900 "setenv fdtaddr 0x00c00000;" \
901 "setenv loadaddr 0x1000000;" \
902 "bootm $loadaddr $ramdiskaddr $fdtaddr"
904 #define CONFIG_HDBOOT \
905 "setenv bootargs root=/dev/$bdev rw " \
906 "console=$consoledev,$baudrate $othbootargs;" \
907 "tftp $loadaddr $bootfile;" \
908 "tftp $fdtaddr $fdtfile;" \
909 "bootm $loadaddr - $fdtaddr"
911 #define CONFIG_NFSBOOTCOMMAND \
912 "setenv bootargs root=/dev/nfs rw " \
913 "nfsroot=$serverip:$rootpath " \
914 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
915 "console=$consoledev,$baudrate $othbootargs;" \
916 "tftp $loadaddr $bootfile;" \
917 "tftp $fdtaddr $fdtfile;" \
918 "bootm $loadaddr - $fdtaddr"
920 #define CONFIG_RAMBOOTCOMMAND \
921 "setenv bootargs root=/dev/ram rw " \
922 "console=$consoledev,$baudrate $othbootargs;" \
923 "tftp $ramdiskaddr $ramdiskfile;" \
924 "tftp $loadaddr $bootfile;" \
925 "tftp $fdtaddr $fdtfile;" \
926 "bootm $loadaddr $ramdiskaddr $fdtaddr"
928 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
930 #include <asm/fsl_secure_boot.h>
932 #endif /* __CONFIG_H */