2 + * Copyright 2014 Freescale Semiconductor, Inc.
4 + * SPDX-License-Identifier: GPL-2.0+
11 * T104x RDB board configuration file
13 #define CONFIG_T104xRDB
14 #define CONFIG_DISPLAY_BOARDINFO
16 #define CONFIG_E500 /* BOOKE e500 family */
17 #include <asm/config_mpc85xx.h>
19 #ifdef CONFIG_RAMBOOT_PBL
21 #ifndef CONFIG_SECURE_BOOT
22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
24 #define CONFIG_SYS_FSL_PBL_PBI \
25 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
28 #ifdef CONFIG_T1040RDB
29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
31 #ifdef CONFIG_T1042RDB_PI
32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
34 #ifdef CONFIG_T1042RDB
35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
37 #ifdef CONFIG_T1040D4RDB
38 #define CONFIG_SYS_FSL_PBL_RCW \
39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
41 #ifdef CONFIG_T1042D4RDB
42 #define CONFIG_SYS_FSL_PBL_RCW \
43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
46 #define CONFIG_SPL_SERIAL_SUPPORT
47 #define CONFIG_SPL_FLUSH_IMAGE
48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
49 #define CONFIG_FSL_LAW /* Use common FSL init code */
50 #define CONFIG_SYS_TEXT_BASE 0x30001000
51 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
52 #define CONFIG_SPL_PAD_TO 0x40000
53 #define CONFIG_SPL_MAX_SIZE 0x28000
54 #ifdef CONFIG_SPL_BUILD
55 #define CONFIG_SPL_SKIP_RELOCATE
56 #define CONFIG_SPL_COMMON_INIT_DDR
57 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
58 #define CONFIG_SYS_NO_FLASH
60 #define RESET_VECTOR_OFFSET 0x27FFC
61 #define BOOT_PAGE_OFFSET 0x27000
64 #define CONFIG_SPL_NAND_SUPPORT
65 #ifdef CONFIG_SECURE_BOOT
66 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
68 * HDR would be appended at end of image and copied to DDR along
71 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
72 CONFIG_U_BOOT_HDR_SIZE)
74 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
76 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
77 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
78 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
80 #define CONFIG_SPL_NAND_BOOT
83 #ifdef CONFIG_SPIFLASH
84 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
85 #define CONFIG_SPL_SPI_SUPPORT
86 #define CONFIG_SPL_SPI_FLASH_SUPPORT
87 #define CONFIG_SPL_SPI_FLASH_MINIMAL
88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
92 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
93 #ifndef CONFIG_SPL_BUILD
94 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
96 #define CONFIG_SPL_SPI_BOOT
100 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
101 #define CONFIG_SPL_MMC_MINIMAL
102 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
103 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
104 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
105 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
106 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
107 #ifndef CONFIG_SPL_BUILD
108 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
110 #define CONFIG_SPL_MMC_BOOT
115 /* High Level Configuration Options */
117 #define CONFIG_E500MC /* BOOKE e500mc family */
118 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
119 #define CONFIG_MP /* support multiple processors */
121 /* support deep sleep */
122 #define CONFIG_DEEP_SLEEP
123 #if defined(CONFIG_DEEP_SLEEP)
124 #define CONFIG_BOARD_EARLY_INIT_F
125 #define CONFIG_SILENT_CONSOLE
128 #ifndef CONFIG_SYS_TEXT_BASE
129 #define CONFIG_SYS_TEXT_BASE 0xeff40000
132 #ifndef CONFIG_RESET_VECTOR_ADDRESS
133 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
136 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
137 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
138 #define CONFIG_FSL_IFC /* Enable IFC Support */
139 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
140 #define CONFIG_PCI /* Enable PCI/PCIE */
141 #define CONFIG_PCI_INDIRECT_BRIDGE
142 #define CONFIG_PCIE1 /* PCIE controller 1 */
143 #define CONFIG_PCIE2 /* PCIE controller 2 */
144 #define CONFIG_PCIE3 /* PCIE controller 3 */
145 #define CONFIG_PCIE4 /* PCIE controller 4 */
147 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
148 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
150 #define CONFIG_FSL_LAW /* Use common FSL init code */
152 #define CONFIG_ENV_OVERWRITE
154 #ifndef CONFIG_SYS_NO_FLASH
155 #define CONFIG_FLASH_CFI_DRIVER
156 #define CONFIG_SYS_FLASH_CFI
157 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
160 #if defined(CONFIG_SPIFLASH)
161 #define CONFIG_SYS_EXTRA_ENV_RELOC
162 #define CONFIG_ENV_IS_IN_SPI_FLASH
163 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
164 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
165 #define CONFIG_ENV_SECT_SIZE 0x10000
166 #elif defined(CONFIG_SDCARD)
167 #define CONFIG_SYS_EXTRA_ENV_RELOC
168 #define CONFIG_ENV_IS_IN_MMC
169 #define CONFIG_SYS_MMC_ENV_DEV 0
170 #define CONFIG_ENV_SIZE 0x2000
171 #define CONFIG_ENV_OFFSET (512 * 0x800)
172 #elif defined(CONFIG_NAND)
173 #ifdef CONFIG_SECURE_BOOT
174 #define CONFIG_RAMBOOT_NAND
175 #define CONFIG_BOOTSCRIPT_COPY_RAM
177 #define CONFIG_SYS_EXTRA_ENV_RELOC
178 #define CONFIG_ENV_IS_IN_NAND
179 #define CONFIG_ENV_SIZE 0x2000
180 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
182 #define CONFIG_ENV_IS_IN_FLASH
183 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
184 #define CONFIG_ENV_SIZE 0x2000
185 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
188 #define CONFIG_SYS_CLK_FREQ 100000000
189 #define CONFIG_DDR_CLK_FREQ 66666666
192 * These can be toggled for performance analysis, otherwise use default.
194 #define CONFIG_SYS_CACHE_STASHING
195 #define CONFIG_BACKSIDE_L2_CACHE
196 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
197 #define CONFIG_BTB /* toggle branch predition */
198 #define CONFIG_DDR_ECC
199 #ifdef CONFIG_DDR_ECC
200 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
201 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
204 #define CONFIG_ENABLE_36BIT_PHYS
206 #define CONFIG_ADDR_MAP
207 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
209 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
210 #define CONFIG_SYS_MEMTEST_END 0x00400000
211 #define CONFIG_SYS_ALT_MEMTEST
212 #define CONFIG_PANIC_HANG /* do not reset board on panic */
215 * Config the L3 Cache as L3 SRAM
217 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
219 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
220 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
221 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
223 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
224 #define CONFIG_SYS_L3_SIZE 256 << 10
225 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
226 #ifdef CONFIG_RAMBOOT_PBL
227 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
229 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
230 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
231 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
232 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
234 #define CONFIG_SYS_DCSRBAR 0xf0000000
235 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
240 #define CONFIG_VERY_BIG_RAM
241 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
242 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
244 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
245 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
246 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
248 #define CONFIG_DDR_SPD
249 #ifndef CONFIG_SYS_FSL_DDR4
250 #define CONFIG_SYS_FSL_DDR3
253 #define CONFIG_SYS_SPD_BUS_NUM 0
254 #define SPD_EEPROM_ADDRESS 0x51
256 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
261 #define CONFIG_SYS_FLASH_BASE 0xe8000000
262 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
264 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
265 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
266 CSPR_PORT_SIZE_16 | \
269 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
274 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
276 /* NOR Flash Timing Params */
277 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
278 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
279 FTIM0_NOR_TEADC(0x5) | \
280 FTIM0_NOR_TEAHC(0x5))
281 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
282 FTIM1_NOR_TRAD_NOR(0x1A) |\
283 FTIM1_NOR_TSEQRAD_NOR(0x13))
284 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
285 FTIM2_NOR_TCH(0x4) | \
286 FTIM2_NOR_TWPH(0x0E) | \
288 #define CONFIG_SYS_NOR_FTIM3 0x0
290 #define CONFIG_SYS_FLASH_QUIET_TEST
291 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
293 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
294 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
295 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
296 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
298 #define CONFIG_SYS_FLASH_EMPTY_INFO
299 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
302 #define CPLD_LBMAP_MASK 0x3F
303 #define CPLD_BANK_SEL_MASK 0x07
304 #define CPLD_BANK_OVERRIDE 0x40
305 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
306 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
307 #define CPLD_LBMAP_RESET 0xFF
308 #define CPLD_LBMAP_SHIFT 0x03
310 #if defined(CONFIG_T1042RDB_PI)
311 #define CPLD_DIU_SEL_DFP 0x80
312 #elif defined(CONFIG_T1042D4RDB)
313 #define CPLD_DIU_SEL_DFP 0xc0
316 #if defined(CONFIG_T1040D4RDB)
317 #define CPLD_INT_MASK_ALL 0xFF
318 #define CPLD_INT_MASK_THERM 0x80
319 #define CPLD_INT_MASK_DVI_DFP 0x40
320 #define CPLD_INT_MASK_QSGMII1 0x20
321 #define CPLD_INT_MASK_QSGMII2 0x10
322 #define CPLD_INT_MASK_SGMI1 0x08
323 #define CPLD_INT_MASK_SGMI2 0x04
324 #define CPLD_INT_MASK_TDMR1 0x02
325 #define CPLD_INT_MASK_TDMR2 0x01
328 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
329 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
330 #define CONFIG_SYS_CSPR2_EXT (0xf)
331 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
335 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
336 #define CONFIG_SYS_CSOR2 0x0
337 /* CPLD Timing parameters for IFC CS2 */
338 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
339 FTIM0_GPCM_TEADC(0x0e) | \
340 FTIM0_GPCM_TEAHC(0x0e))
341 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
342 FTIM1_GPCM_TRAD(0x1f))
343 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
344 FTIM2_GPCM_TCH(0x8) | \
345 FTIM2_GPCM_TWP(0x1f))
346 #define CONFIG_SYS_CS2_FTIM3 0x0
348 /* NAND Flash on IFC */
349 #define CONFIG_NAND_FSL_IFC
350 #define CONFIG_SYS_NAND_BASE 0xff800000
351 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
353 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
354 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
355 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
356 | CSPR_MSEL_NAND /* MSEL = NAND */ \
358 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
360 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
361 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
362 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
363 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
364 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
365 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
366 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
368 #define CONFIG_SYS_NAND_ONFI_DETECTION
370 /* ONFI NAND Flash mode0 Timing Params */
371 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
372 FTIM0_NAND_TWP(0x18) | \
373 FTIM0_NAND_TWCHT(0x07) | \
374 FTIM0_NAND_TWH(0x0a))
375 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
376 FTIM1_NAND_TWBE(0x39) | \
377 FTIM1_NAND_TRR(0x0e) | \
378 FTIM1_NAND_TRP(0x18))
379 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
380 FTIM2_NAND_TREH(0x0a) | \
381 FTIM2_NAND_TWHRE(0x1e))
382 #define CONFIG_SYS_NAND_FTIM3 0x0
384 #define CONFIG_SYS_NAND_DDR_LAW 11
385 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
386 #define CONFIG_SYS_MAX_NAND_DEVICE 1
387 #define CONFIG_CMD_NAND
389 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
391 #if defined(CONFIG_NAND)
392 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
393 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
394 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
395 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
396 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
397 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
398 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
399 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
400 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
401 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
402 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
403 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
404 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
405 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
406 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
407 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
409 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
410 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
411 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
412 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
413 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
414 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
415 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
416 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
417 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
418 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
419 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
420 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
421 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
422 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
423 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
424 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
427 #ifdef CONFIG_SPL_BUILD
428 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
430 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
433 #if defined(CONFIG_RAMBOOT_PBL)
434 #define CONFIG_SYS_RAMBOOT
437 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
438 #if defined(CONFIG_NAND)
439 #define CONFIG_A008044_WORKAROUND
443 #define CONFIG_BOARD_EARLY_INIT_R
444 #define CONFIG_MISC_INIT_R
446 #define CONFIG_HWCONFIG
448 /* define to use L1 as initial stack */
449 #define CONFIG_L1_INIT_RAM
450 #define CONFIG_SYS_INIT_RAM_LOCK
451 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
454 /* The assembler doesn't like typecast */
455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
456 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
457 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
458 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
460 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
461 GENERATED_GBL_DATA_SIZE)
462 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
464 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
465 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
467 /* Serial Port - controlled on board with jumper J8
471 #define CONFIG_CONS_INDEX 1
472 #define CONFIG_SYS_NS16550_SERIAL
473 #define CONFIG_SYS_NS16550_REG_SIZE 1
474 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
476 #define CONFIG_SYS_BAUDRATE_TABLE \
477 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
479 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
480 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
481 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
482 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
483 #ifndef CONFIG_SPL_BUILD
484 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
487 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
489 #define CONFIG_FSL_DIU_FB
491 #ifdef CONFIG_FSL_DIU_FB
492 #define CONFIG_FSL_DIU_CH7301
493 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
495 #define CONFIG_CMD_BMP
496 #define CONFIG_CFB_CONSOLE
497 #define CONFIG_CFB_CONSOLE_ANSI
498 #define CONFIG_VIDEO_SW_CURSOR
499 #define CONFIG_VGA_AS_SINGLE_DEVICE
500 #define CONFIG_VIDEO_LOGO
501 #define CONFIG_VIDEO_BMP_LOGO
506 #define CONFIG_SYS_I2C
507 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
508 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
509 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
510 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
511 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
512 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
513 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
514 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
515 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
516 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
517 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
518 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
519 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
521 /* I2C bus multiplexer */
522 #define I2C_MUX_PCA_ADDR 0x70
523 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
524 #define I2C_MUX_CH_DEFAULT 0x8
527 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
528 /* LDI/DVI Encoder for display */
529 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
530 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
536 #define CONFIG_RTC_DS1337 1
537 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
540 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
544 * eSPI - Enhanced SPI
546 #define CONFIG_SPI_FLASH_BAR
547 #define CONFIG_SF_DEFAULT_SPEED 10000000
548 #define CONFIG_SF_DEFAULT_MODE 0
549 #define CONFIG_ENV_SPI_BUS 0
550 #define CONFIG_ENV_SPI_CS 0
551 #define CONFIG_ENV_SPI_MAX_HZ 10000000
552 #define CONFIG_ENV_SPI_MODE 0
556 * Memory space is mapped 1-1, but I/O space must start from 0.
560 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
562 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
563 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
564 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
565 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
566 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
567 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
568 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
569 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
572 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
574 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
575 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
576 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
577 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
578 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
579 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
580 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
581 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
584 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
586 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
587 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
588 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
589 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
590 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
591 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
592 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
593 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
596 /* controller 4, Base address 203000 */
598 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
599 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
600 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
601 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
602 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
603 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
604 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
605 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
608 #define CONFIG_PCI_PNP /* do pci plug-and-play */
610 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
611 #define CONFIG_DOS_PARTITION
612 #endif /* CONFIG_PCI */
615 #define CONFIG_FSL_SATA_V2
616 #ifdef CONFIG_FSL_SATA_V2
617 #define CONFIG_LIBATA
618 #define CONFIG_FSL_SATA
620 #define CONFIG_SYS_SATA_MAX_DEVICE 1
622 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
623 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
626 #define CONFIG_CMD_SATA
627 #define CONFIG_DOS_PARTITION
633 #define CONFIG_HAS_FSL_DR_USB
635 #ifdef CONFIG_HAS_FSL_DR_USB
636 #define CONFIG_USB_EHCI
638 #ifdef CONFIG_USB_EHCI
639 #define CONFIG_USB_EHCI_FSL
640 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
647 #define CONFIG_FSL_ESDHC
648 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
649 #define CONFIG_GENERIC_MMC
650 #define CONFIG_DOS_PARTITION
654 #ifndef CONFIG_NOBQFMAN
655 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
656 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
657 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
658 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
659 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
660 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
661 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
662 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
663 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
664 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
665 CONFIG_SYS_BMAN_CENA_SIZE)
666 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
667 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
668 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
669 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
670 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
671 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
672 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
673 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
674 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
675 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
676 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
677 CONFIG_SYS_QMAN_CENA_SIZE)
678 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
679 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
681 #define CONFIG_SYS_DPAA_FMAN
682 #define CONFIG_SYS_DPAA_PME
684 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
689 /* Default address of microcode for the Linux Fman driver */
690 #if defined(CONFIG_SPIFLASH)
692 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
693 * env, so we got 0x110000.
695 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
696 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
697 #elif defined(CONFIG_SDCARD)
699 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
700 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
701 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
703 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
704 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
705 #elif defined(CONFIG_NAND)
706 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
707 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
709 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
710 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
713 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
714 #if defined(CONFIG_SPIFLASH)
715 #define CONFIG_SYS_QE_FW_ADDR 0x130000
716 #elif defined(CONFIG_SDCARD)
717 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
718 #elif defined(CONFIG_NAND)
719 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
721 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
725 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
726 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
727 #endif /* CONFIG_NOBQFMAN */
729 #ifdef CONFIG_SYS_DPAA_FMAN
730 #define CONFIG_FMAN_ENET
731 #define CONFIG_PHY_VITESSE
732 #define CONFIG_PHY_REALTEK
735 #ifdef CONFIG_FMAN_ENET
736 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
737 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
738 #elif defined(CONFIG_T1040D4RDB)
739 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
740 #elif defined(CONFIG_T1042D4RDB)
741 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
742 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
743 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
746 #ifdef CONFIG_T104XD4RDB
747 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
748 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
750 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
751 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
754 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
755 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
756 #define CONFIG_VSC9953
757 #define CONFIG_CMD_ETHSW
758 #ifdef CONFIG_T1040RDB
759 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
760 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
762 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
763 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
767 #define CONFIG_MII /* MII PHY management */
768 #define CONFIG_ETHPRIME "FM1@DTSEC4"
769 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
775 #define CONFIG_LOADS_ECHO /* echo on for serial download */
776 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
779 * Command line configuration.
781 #ifdef CONFIG_T1042RDB_PI
782 #define CONFIG_CMD_DATE
784 #define CONFIG_CMD_ERRATA
785 #define CONFIG_CMD_IRQ
786 #define CONFIG_CMD_REGINFO
789 #define CONFIG_CMD_PCI
792 /* Hash command with SHA acceleration supported in hardware */
793 #ifdef CONFIG_FSL_CAAM
794 #define CONFIG_CMD_HASH
795 #define CONFIG_SHA_HW_ACCEL
799 * Miscellaneous configurable options
801 #define CONFIG_SYS_LONGHELP /* undef to save memory */
802 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
803 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
804 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
805 #ifdef CONFIG_CMD_KGDB
806 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
808 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
810 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
811 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
812 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
815 * For booting Linux, the board info and command line data
816 * have to be in the first 64 MB of memory, since this is
817 * the maximum mapped by the Linux kernel during initialization.
819 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
820 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
822 #ifdef CONFIG_CMD_KGDB
823 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
827 * Dynamic MTD Partition support with mtdparts
829 #ifndef CONFIG_SYS_NO_FLASH
830 #define CONFIG_MTD_DEVICE
831 #define CONFIG_MTD_PARTITIONS
832 #define CONFIG_CMD_MTDPARTS
833 #define CONFIG_FLASH_CFI_MTD
834 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
836 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
837 "128k(dtb),96m(fs),-(user);"\
838 "fff800000.flash:2m(uboot),9m(kernel),"\
839 "128k(dtb),96m(fs),-(user);spife110000.0:" \
840 "2m(uboot),9m(kernel),128k(dtb),-(user)"
844 * Environment Configuration
846 #define CONFIG_ROOTPATH "/opt/nfsroot"
847 #define CONFIG_BOOTFILE "uImage"
848 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
850 /* default location for tftp and bootm */
851 #define CONFIG_LOADADDR 1000000
854 #define CONFIG_BAUDRATE 115200
856 #define __USB_PHY_TYPE utmi
857 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
859 #ifdef CONFIG_T1040RDB
860 #define FDTFILE "t1040rdb/t1040rdb.dtb"
861 #elif defined(CONFIG_T1042RDB_PI)
862 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
863 #elif defined(CONFIG_T1042RDB)
864 #define FDTFILE "t1042rdb/t1042rdb.dtb"
865 #elif defined(CONFIG_T1040D4RDB)
866 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
867 #elif defined(CONFIG_T1042D4RDB)
868 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
871 #ifdef CONFIG_FSL_DIU_FB
872 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
874 #define DIU_ENVIRONMENT
877 #define CONFIG_EXTRA_ENV_SETTINGS \
878 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
879 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
880 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
882 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
883 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
884 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
885 "tftpflash=tftpboot $loadaddr $uboot && " \
886 "protect off $ubootaddr +$filesize && " \
887 "erase $ubootaddr +$filesize && " \
888 "cp.b $loadaddr $ubootaddr $filesize && " \
889 "protect on $ubootaddr +$filesize && " \
890 "cmp.b $loadaddr $ubootaddr $filesize\0" \
891 "consoledev=ttyS0\0" \
892 "ramdiskaddr=2000000\0" \
893 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
894 "fdtaddr=1e00000\0" \
895 "fdtfile=" __stringify(FDTFILE) "\0" \
898 #define CONFIG_LINUX \
899 "setenv bootargs root=/dev/ram rw " \
900 "console=$consoledev,$baudrate $othbootargs;" \
901 "setenv ramdiskaddr 0x02000000;" \
902 "setenv fdtaddr 0x00c00000;" \
903 "setenv loadaddr 0x1000000;" \
904 "bootm $loadaddr $ramdiskaddr $fdtaddr"
906 #define CONFIG_HDBOOT \
907 "setenv bootargs root=/dev/$bdev rw " \
908 "console=$consoledev,$baudrate $othbootargs;" \
909 "tftp $loadaddr $bootfile;" \
910 "tftp $fdtaddr $fdtfile;" \
911 "bootm $loadaddr - $fdtaddr"
913 #define CONFIG_NFSBOOTCOMMAND \
914 "setenv bootargs root=/dev/nfs rw " \
915 "nfsroot=$serverip:$rootpath " \
916 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
917 "console=$consoledev,$baudrate $othbootargs;" \
918 "tftp $loadaddr $bootfile;" \
919 "tftp $fdtaddr $fdtfile;" \
920 "bootm $loadaddr - $fdtaddr"
922 #define CONFIG_RAMBOOTCOMMAND \
923 "setenv bootargs root=/dev/ram rw " \
924 "console=$consoledev,$baudrate $othbootargs;" \
925 "tftp $ramdiskaddr $ramdiskfile;" \
926 "tftp $loadaddr $bootfile;" \
927 "tftp $fdtaddr $fdtfile;" \
928 "bootm $loadaddr $ramdiskaddr $fdtaddr"
930 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
932 #include <asm/fsl_secure_boot.h>
934 #endif /* __CONFIG_H */