2 + * Copyright 2014 Freescale Semiconductor, Inc.
4 + * SPDX-License-Identifier: GPL-2.0+
11 * T104x RDB board configuration file
13 #include <asm/config_mpc85xx.h>
15 #ifdef CONFIG_RAMBOOT_PBL
17 #ifndef CONFIG_SECURE_BOOT
18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
20 #define CONFIG_SYS_FSL_PBL_PBI \
21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
27 #define CONFIG_SPL_PAD_TO 0x40000
28 #define CONFIG_SPL_MAX_SIZE 0x28000
29 #ifdef CONFIG_SPL_BUILD
30 #define CONFIG_SPL_SKIP_RELOCATE
31 #define CONFIG_SPL_COMMON_INIT_DDR
32 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
34 #define RESET_VECTOR_OFFSET 0x27FFC
35 #define BOOT_PAGE_OFFSET 0x27000
38 #ifdef CONFIG_SECURE_BOOT
39 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
41 * HDR would be appended at end of image and copied to DDR along
44 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
45 CONFIG_U_BOOT_HDR_SIZE)
47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
50 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
53 #ifdef CONFIG_TARGET_T1040RDB
54 #define CONFIG_SYS_FSL_PBL_RCW \
55 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
57 #ifdef CONFIG_TARGET_T1042RDB_PI
58 #define CONFIG_SYS_FSL_PBL_RCW \
59 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
61 #ifdef CONFIG_TARGET_T1042RDB
62 #define CONFIG_SYS_FSL_PBL_RCW \
63 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
65 #ifdef CONFIG_TARGET_T1040D4RDB
66 #define CONFIG_SYS_FSL_PBL_RCW \
67 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
69 #ifdef CONFIG_TARGET_T1042D4RDB
70 #define CONFIG_SYS_FSL_PBL_RCW \
71 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
73 #define CONFIG_SPL_NAND_BOOT
76 #ifdef CONFIG_SPIFLASH
77 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
78 #define CONFIG_SPL_SPI_FLASH_MINIMAL
79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
84 #ifndef CONFIG_SPL_BUILD
85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
87 #ifdef CONFIG_TARGET_T1040RDB
88 #define CONFIG_SYS_FSL_PBL_RCW \
89 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
91 #ifdef CONFIG_TARGET_T1042RDB_PI
92 #define CONFIG_SYS_FSL_PBL_RCW \
93 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
95 #ifdef CONFIG_TARGET_T1042RDB
96 #define CONFIG_SYS_FSL_PBL_RCW \
97 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
99 #ifdef CONFIG_TARGET_T1040D4RDB
100 #define CONFIG_SYS_FSL_PBL_RCW \
101 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
103 #ifdef CONFIG_TARGET_T1042D4RDB
104 #define CONFIG_SYS_FSL_PBL_RCW \
105 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
107 #define CONFIG_SPL_SPI_BOOT
111 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
112 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
113 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
114 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
115 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
116 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
117 #ifndef CONFIG_SPL_BUILD
118 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
120 #ifdef CONFIG_TARGET_T1040RDB
121 #define CONFIG_SYS_FSL_PBL_RCW \
122 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
124 #ifdef CONFIG_TARGET_T1042RDB_PI
125 #define CONFIG_SYS_FSL_PBL_RCW \
126 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
128 #ifdef CONFIG_TARGET_T1042RDB
129 #define CONFIG_SYS_FSL_PBL_RCW \
130 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
132 #ifdef CONFIG_TARGET_T1040D4RDB
133 #define CONFIG_SYS_FSL_PBL_RCW \
134 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
136 #ifdef CONFIG_TARGET_T1042D4RDB
137 #define CONFIG_SYS_FSL_PBL_RCW \
138 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
140 #define CONFIG_SPL_MMC_BOOT
145 /* High Level Configuration Options */
146 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
147 #define CONFIG_MP /* support multiple processors */
149 /* support deep sleep */
150 #define CONFIG_DEEP_SLEEP
152 #ifndef CONFIG_RESET_VECTOR_ADDRESS
153 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
156 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
157 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
158 #define CONFIG_PCI_INDIRECT_BRIDGE
159 #define CONFIG_PCIE1 /* PCIE controller 1 */
160 #define CONFIG_PCIE2 /* PCIE controller 2 */
161 #define CONFIG_PCIE3 /* PCIE controller 3 */
162 #define CONFIG_PCIE4 /* PCIE controller 4 */
164 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
165 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
167 #define CONFIG_ENV_OVERWRITE
169 #ifdef CONFIG_MTD_NOR_FLASH
170 #define CONFIG_FLASH_CFI_DRIVER
171 #define CONFIG_SYS_FLASH_CFI
172 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
175 #if defined(CONFIG_SPIFLASH)
176 #define CONFIG_SYS_EXTRA_ENV_RELOC
177 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
178 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
179 #define CONFIG_ENV_SECT_SIZE 0x10000
180 #elif defined(CONFIG_SDCARD)
181 #define CONFIG_SYS_EXTRA_ENV_RELOC
182 #define CONFIG_SYS_MMC_ENV_DEV 0
183 #define CONFIG_ENV_SIZE 0x2000
184 #define CONFIG_ENV_OFFSET (512 * 0x800)
185 #elif defined(CONFIG_NAND)
186 #ifdef CONFIG_SECURE_BOOT
187 #define CONFIG_RAMBOOT_NAND
188 #define CONFIG_BOOTSCRIPT_COPY_RAM
190 #define CONFIG_SYS_EXTRA_ENV_RELOC
191 #define CONFIG_ENV_SIZE 0x2000
192 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
194 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
195 #define CONFIG_ENV_SIZE 0x2000
196 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
199 #define CONFIG_SYS_CLK_FREQ 100000000
200 #define CONFIG_DDR_CLK_FREQ 66666666
203 * These can be toggled for performance analysis, otherwise use default.
205 #define CONFIG_SYS_CACHE_STASHING
206 #define CONFIG_BACKSIDE_L2_CACHE
207 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
208 #define CONFIG_BTB /* toggle branch predition */
209 #define CONFIG_DDR_ECC
210 #ifdef CONFIG_DDR_ECC
211 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
212 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
215 #define CONFIG_ENABLE_36BIT_PHYS
217 #define CONFIG_ADDR_MAP
218 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
220 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
221 #define CONFIG_SYS_MEMTEST_END 0x00400000
224 * Config the L3 Cache as L3 SRAM
226 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
228 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
229 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
230 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
232 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
233 #define CONFIG_SYS_L3_SIZE 256 << 10
234 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
235 #ifdef CONFIG_RAMBOOT_PBL
236 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
238 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
239 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
240 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
241 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
243 #define CONFIG_SYS_DCSRBAR 0xf0000000
244 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
249 #define CONFIG_VERY_BIG_RAM
250 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
251 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
253 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
254 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
256 #define CONFIG_DDR_SPD
258 #define CONFIG_SYS_SPD_BUS_NUM 0
259 #define SPD_EEPROM_ADDRESS 0x51
261 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
266 #define CONFIG_SYS_FLASH_BASE 0xe8000000
267 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
269 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
270 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
271 CSPR_PORT_SIZE_16 | \
274 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
279 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
281 /* NOR Flash Timing Params */
282 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
283 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
284 FTIM0_NOR_TEADC(0x5) | \
285 FTIM0_NOR_TEAHC(0x5))
286 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
287 FTIM1_NOR_TRAD_NOR(0x1A) |\
288 FTIM1_NOR_TSEQRAD_NOR(0x13))
289 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
290 FTIM2_NOR_TCH(0x4) | \
291 FTIM2_NOR_TWPH(0x0E) | \
293 #define CONFIG_SYS_NOR_FTIM3 0x0
295 #define CONFIG_SYS_FLASH_QUIET_TEST
296 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
298 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
299 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
300 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
301 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
303 #define CONFIG_SYS_FLASH_EMPTY_INFO
304 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
307 #define CPLD_LBMAP_MASK 0x3F
308 #define CPLD_BANK_SEL_MASK 0x07
309 #define CPLD_BANK_OVERRIDE 0x40
310 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
311 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
312 #define CPLD_LBMAP_RESET 0xFF
313 #define CPLD_LBMAP_SHIFT 0x03
315 #if defined(CONFIG_TARGET_T1042RDB_PI)
316 #define CPLD_DIU_SEL_DFP 0x80
317 #elif defined(CONFIG_TARGET_T1042D4RDB)
318 #define CPLD_DIU_SEL_DFP 0xc0
321 #if defined(CONFIG_TARGET_T1040D4RDB)
322 #define CPLD_INT_MASK_ALL 0xFF
323 #define CPLD_INT_MASK_THERM 0x80
324 #define CPLD_INT_MASK_DVI_DFP 0x40
325 #define CPLD_INT_MASK_QSGMII1 0x20
326 #define CPLD_INT_MASK_QSGMII2 0x10
327 #define CPLD_INT_MASK_SGMI1 0x08
328 #define CPLD_INT_MASK_SGMI2 0x04
329 #define CPLD_INT_MASK_TDMR1 0x02
330 #define CPLD_INT_MASK_TDMR2 0x01
333 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
334 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
335 #define CONFIG_SYS_CSPR2_EXT (0xf)
336 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
340 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
341 #define CONFIG_SYS_CSOR2 0x0
342 /* CPLD Timing parameters for IFC CS2 */
343 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
344 FTIM0_GPCM_TEADC(0x0e) | \
345 FTIM0_GPCM_TEAHC(0x0e))
346 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
347 FTIM1_GPCM_TRAD(0x1f))
348 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
349 FTIM2_GPCM_TCH(0x8) | \
350 FTIM2_GPCM_TWP(0x1f))
351 #define CONFIG_SYS_CS2_FTIM3 0x0
353 /* NAND Flash on IFC */
354 #define CONFIG_NAND_FSL_IFC
355 #define CONFIG_SYS_NAND_BASE 0xff800000
356 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
358 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
359 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
360 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
361 | CSPR_MSEL_NAND /* MSEL = NAND */ \
363 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
365 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
366 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
367 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
368 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
369 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
370 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
371 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
373 #define CONFIG_SYS_NAND_ONFI_DETECTION
375 /* ONFI NAND Flash mode0 Timing Params */
376 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
377 FTIM0_NAND_TWP(0x18) | \
378 FTIM0_NAND_TWCHT(0x07) | \
379 FTIM0_NAND_TWH(0x0a))
380 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
381 FTIM1_NAND_TWBE(0x39) | \
382 FTIM1_NAND_TRR(0x0e) | \
383 FTIM1_NAND_TRP(0x18))
384 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
385 FTIM2_NAND_TREH(0x0a) | \
386 FTIM2_NAND_TWHRE(0x1e))
387 #define CONFIG_SYS_NAND_FTIM3 0x0
389 #define CONFIG_SYS_NAND_DDR_LAW 11
390 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
391 #define CONFIG_SYS_MAX_NAND_DEVICE 1
393 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
395 #if defined(CONFIG_NAND)
396 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
397 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
398 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
399 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
400 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
401 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
402 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
403 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
404 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
405 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
406 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
407 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
408 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
409 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
410 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
411 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
413 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
414 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
415 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
416 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
417 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
418 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
419 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
420 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
421 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
422 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
423 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
424 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
425 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
426 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
427 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
428 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
431 #ifdef CONFIG_SPL_BUILD
432 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
434 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
437 #if defined(CONFIG_RAMBOOT_PBL)
438 #define CONFIG_SYS_RAMBOOT
441 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
442 #if defined(CONFIG_NAND)
443 #define CONFIG_A008044_WORKAROUND
447 #define CONFIG_BOARD_EARLY_INIT_R
448 #define CONFIG_MISC_INIT_R
450 #define CONFIG_HWCONFIG
452 /* define to use L1 as initial stack */
453 #define CONFIG_L1_INIT_RAM
454 #define CONFIG_SYS_INIT_RAM_LOCK
455 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
458 /* The assembler doesn't like typecast */
459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
460 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
461 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
462 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
464 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
465 GENERATED_GBL_DATA_SIZE)
466 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
468 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
469 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
471 /* Serial Port - controlled on board with jumper J8
475 #define CONFIG_SYS_NS16550_SERIAL
476 #define CONFIG_SYS_NS16550_REG_SIZE 1
477 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
479 #define CONFIG_SYS_BAUDRATE_TABLE \
480 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
482 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
483 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
484 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
485 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
487 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
489 #define CONFIG_FSL_DIU_FB
491 #ifdef CONFIG_FSL_DIU_FB
492 #define CONFIG_FSL_DIU_CH7301
493 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
494 #define CONFIG_VIDEO_LOGO
495 #define CONFIG_VIDEO_BMP_LOGO
500 #define CONFIG_SYS_I2C
501 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
502 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
503 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
504 #define CONFIG_SYS_FSL_I2C3_SPEED 400000
505 #define CONFIG_SYS_FSL_I2C4_SPEED 400000
506 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
507 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
508 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
509 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
510 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
511 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
512 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
513 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
515 /* I2C bus multiplexer */
516 #define I2C_MUX_PCA_ADDR 0x70
517 #define I2C_MUX_CH_DEFAULT 0x8
519 #if defined(CONFIG_TARGET_T1042RDB_PI) || \
520 defined(CONFIG_TARGET_T1040D4RDB) || \
521 defined(CONFIG_TARGET_T1042D4RDB)
522 /* LDI/DVI Encoder for display */
523 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
524 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
530 #define CONFIG_RTC_DS1337 1
531 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
534 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
538 * eSPI - Enhanced SPI
540 #define CONFIG_SPI_FLASH_BAR
541 #define CONFIG_SF_DEFAULT_SPEED 10000000
542 #define CONFIG_SF_DEFAULT_MODE 0
543 #define CONFIG_ENV_SPI_BUS 0
544 #define CONFIG_ENV_SPI_CS 0
545 #define CONFIG_ENV_SPI_MAX_HZ 10000000
546 #define CONFIG_ENV_SPI_MODE 0
550 * Memory space is mapped 1-1, but I/O space must start from 0.
554 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
556 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
557 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
558 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
559 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
560 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
561 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
562 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
563 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
566 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
568 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
569 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
570 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
571 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
572 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
573 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
574 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
575 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
578 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
580 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
581 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
582 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
583 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
584 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
585 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
586 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
587 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
590 /* controller 4, Base address 203000 */
592 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
593 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
594 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
595 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
596 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
597 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
598 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
599 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
602 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
603 #endif /* CONFIG_PCI */
606 #define CONFIG_FSL_SATA_V2
607 #ifdef CONFIG_FSL_SATA_V2
608 #define CONFIG_SYS_SATA_MAX_DEVICE 1
610 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
611 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
619 #define CONFIG_HAS_FSL_DR_USB
621 #ifdef CONFIG_HAS_FSL_DR_USB
622 #ifdef CONFIG_USB_EHCI_HCD
623 #define CONFIG_USB_EHCI_FSL
624 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
625 #define CONFIG_EHCI_DESC_BIG_ENDIAN
630 #define CONFIG_FSL_ESDHC
631 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
635 #ifndef CONFIG_NOBQFMAN
636 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
637 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
638 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
639 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
640 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
641 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
642 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
643 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
644 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
645 CONFIG_SYS_BMAN_CENA_SIZE)
646 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
647 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
648 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
649 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
650 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
651 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
652 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
653 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
654 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
655 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
656 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
657 CONFIG_SYS_QMAN_CENA_SIZE)
658 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
659 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
661 #define CONFIG_SYS_DPAA_FMAN
662 #define CONFIG_SYS_DPAA_PME
667 /* Default address of microcode for the Linux Fman driver */
668 #if defined(CONFIG_SPIFLASH)
670 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
671 * env, so we got 0x110000.
673 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
674 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
675 #elif defined(CONFIG_SDCARD)
677 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
678 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
679 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
681 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
682 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
683 #elif defined(CONFIG_NAND)
684 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
685 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
687 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
688 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
691 #if defined(CONFIG_SPIFLASH)
692 #define CONFIG_SYS_QE_FW_ADDR 0x130000
693 #elif defined(CONFIG_SDCARD)
694 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
695 #elif defined(CONFIG_NAND)
696 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
698 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
701 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
702 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
703 #endif /* CONFIG_NOBQFMAN */
705 #ifdef CONFIG_SYS_DPAA_FMAN
706 #define CONFIG_FMAN_ENET
707 #define CONFIG_PHY_VITESSE
708 #define CONFIG_PHY_REALTEK
711 #ifdef CONFIG_FMAN_ENET
712 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
713 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
714 #elif defined(CONFIG_TARGET_T1040D4RDB)
715 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
716 #elif defined(CONFIG_TARGET_T1042D4RDB)
717 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
718 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
719 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
722 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
723 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
724 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
726 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
727 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
730 /* Enable VSC9953 L2 Switch driver on T1040 SoC */
731 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
732 #define CONFIG_VSC9953
733 #ifdef CONFIG_TARGET_T1040RDB
734 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
735 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
737 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
738 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
742 #define CONFIG_MII /* MII PHY management */
743 #define CONFIG_ETHPRIME "FM1@DTSEC4"
749 #define CONFIG_LOADS_ECHO /* echo on for serial download */
750 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
753 * Miscellaneous configurable options
755 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
758 * For booting Linux, the board info and command line data
759 * have to be in the first 64 MB of memory, since this is
760 * the maximum mapped by the Linux kernel during initialization.
762 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
763 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
765 #ifdef CONFIG_CMD_KGDB
766 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
770 * Dynamic MTD Partition support with mtdparts
772 #ifdef CONFIG_MTD_NOR_FLASH
773 #define CONFIG_MTD_DEVICE
774 #define CONFIG_MTD_PARTITIONS
775 #define CONFIG_FLASH_CFI_MTD
779 * Environment Configuration
781 #define CONFIG_ROOTPATH "/opt/nfsroot"
782 #define CONFIG_BOOTFILE "uImage"
783 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
785 /* default location for tftp and bootm */
786 #define CONFIG_LOADADDR 1000000
788 #define __USB_PHY_TYPE utmi
789 #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
791 #ifdef CONFIG_TARGET_T1040RDB
792 #define FDTFILE "t1040rdb/t1040rdb.dtb"
793 #elif defined(CONFIG_TARGET_T1042RDB_PI)
794 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
795 #elif defined(CONFIG_TARGET_T1042RDB)
796 #define FDTFILE "t1042rdb/t1042rdb.dtb"
797 #elif defined(CONFIG_TARGET_T1040D4RDB)
798 #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
799 #elif defined(CONFIG_TARGET_T1042D4RDB)
800 #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
803 #ifdef CONFIG_FSL_DIU_FB
804 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
806 #define DIU_ENVIRONMENT
809 #define CONFIG_EXTRA_ENV_SETTINGS \
810 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
811 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
812 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
814 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
815 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
816 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
817 "tftpflash=tftpboot $loadaddr $uboot && " \
818 "protect off $ubootaddr +$filesize && " \
819 "erase $ubootaddr +$filesize && " \
820 "cp.b $loadaddr $ubootaddr $filesize && " \
821 "protect on $ubootaddr +$filesize && " \
822 "cmp.b $loadaddr $ubootaddr $filesize\0" \
823 "consoledev=ttyS0\0" \
824 "ramdiskaddr=2000000\0" \
825 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
826 "fdtaddr=1e00000\0" \
827 "fdtfile=" __stringify(FDTFILE) "\0" \
830 #define CONFIG_LINUX \
831 "setenv bootargs root=/dev/ram rw " \
832 "console=$consoledev,$baudrate $othbootargs;" \
833 "setenv ramdiskaddr 0x02000000;" \
834 "setenv fdtaddr 0x00c00000;" \
835 "setenv loadaddr 0x1000000;" \
836 "bootm $loadaddr $ramdiskaddr $fdtaddr"
838 #define CONFIG_HDBOOT \
839 "setenv bootargs root=/dev/$bdev rw " \
840 "console=$consoledev,$baudrate $othbootargs;" \
841 "tftp $loadaddr $bootfile;" \
842 "tftp $fdtaddr $fdtfile;" \
843 "bootm $loadaddr - $fdtaddr"
845 #define CONFIG_NFSBOOTCOMMAND \
846 "setenv bootargs root=/dev/nfs rw " \
847 "nfsroot=$serverip:$rootpath " \
848 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
849 "console=$consoledev,$baudrate $othbootargs;" \
850 "tftp $loadaddr $bootfile;" \
851 "tftp $fdtaddr $fdtfile;" \
852 "bootm $loadaddr - $fdtaddr"
854 #define CONFIG_RAMBOOTCOMMAND \
855 "setenv bootargs root=/dev/ram rw " \
856 "console=$consoledev,$baudrate $othbootargs;" \
857 "tftp $ramdiskaddr $ramdiskfile;" \
858 "tftp $loadaddr $bootfile;" \
859 "tftp $fdtaddr $fdtfile;" \
860 "bootm $loadaddr $ramdiskaddr $fdtaddr"
862 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
864 #include <asm/fsl_secure_boot.h>
866 #endif /* __CONFIG_H */