2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 RDB board configuration file
13 #define CONFIG_FSL_SATA_V2
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
18 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26 #define CONFIG_SYS_TEXT_BASE 0x00201000
27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
28 #define CONFIG_SPL_PAD_TO 0x40000
29 #define CONFIG_SPL_MAX_SIZE 0x28000
30 #define RESET_VECTOR_OFFSET 0x27FFC
31 #define BOOT_PAGE_OFFSET 0x27000
34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
35 #define CONFIG_SPL_MMC_MINIMAL
36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
40 #ifndef CONFIG_SPL_BUILD
41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
45 #define CONFIG_SPL_MMC_BOOT
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SPL_SKIP_RELOCATE
50 #define CONFIG_SPL_COMMON_INIT_DDR
51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
55 #endif /* CONFIG_RAMBOOT_PBL */
57 #define CONFIG_DDR_ECC
59 #define CONFIG_CMD_REGINFO
61 /* High Level Configuration Options */
62 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
63 #define CONFIG_MP /* support multiple processors */
65 #ifndef CONFIG_SYS_TEXT_BASE
66 #define CONFIG_SYS_TEXT_BASE 0xeff40000
69 #ifndef CONFIG_RESET_VECTOR_ADDRESS
70 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
73 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
74 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
75 #define CONFIG_PCIE1 /* PCIE controller 1 */
76 #define CONFIG_PCIE2 /* PCIE controller 2 */
77 #define CONFIG_PCIE3 /* PCIE controller 3 */
78 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
79 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
81 #define CONFIG_ENV_OVERWRITE
84 * These can be toggled for performance analysis, otherwise use default.
86 #define CONFIG_SYS_CACHE_STASHING
87 #define CONFIG_BTB /* toggle branch predition */
89 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
90 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
93 #define CONFIG_ENABLE_36BIT_PHYS
95 #define CONFIG_ADDR_MAP
96 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
98 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
99 #define CONFIG_SYS_MEMTEST_END 0x00400000
100 #define CONFIG_SYS_ALT_MEMTEST
101 #define CONFIG_PANIC_HANG /* do not reset board on panic */
104 * Config the L3 Cache as L3 SRAM
106 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
107 #define CONFIG_SYS_L3_SIZE (512 << 10)
108 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
109 #ifdef CONFIG_RAMBOOT_PBL
110 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
112 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
113 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
114 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
115 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
117 #define CONFIG_SYS_DCSRBAR 0xf0000000
118 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
123 #define CONFIG_VERY_BIG_RAM
124 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
125 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
127 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
128 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
129 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
131 #define CONFIG_DDR_SPD
136 #define CONFIG_SYS_FLASH_BASE 0xe0000000
137 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
139 #ifdef CONFIG_SPL_BUILD
140 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
145 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
146 #define CONFIG_MISC_INIT_R
148 #define CONFIG_HWCONFIG
150 /* define to use L1 as initial stack */
151 #define CONFIG_L1_INIT_RAM
152 #define CONFIG_SYS_INIT_RAM_LOCK
153 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
154 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
155 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
156 /* The assembler doesn't like typecast */
157 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
158 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
159 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
160 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
162 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
163 GENERATED_GBL_DATA_SIZE)
164 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
166 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
167 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
169 /* Serial Port - controlled on board with jumper J8
173 #define CONFIG_CONS_INDEX 1
174 #define CONFIG_SYS_NS16550_SERIAL
175 #define CONFIG_SYS_NS16550_REG_SIZE 1
176 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
178 #define CONFIG_SYS_BAUDRATE_TABLE \
179 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
181 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
182 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
183 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
184 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
187 #define CONFIG_SYS_I2C
188 #define CONFIG_SYS_I2C_FSL
189 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
190 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
191 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
192 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
196 * Memory space is mapped 1-1, but I/O space must start from 0.
199 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
200 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
201 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
202 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
203 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
204 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
205 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
206 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
207 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
209 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
210 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
211 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
212 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
213 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
214 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
215 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
216 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
217 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
219 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
220 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
221 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
222 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
223 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
224 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
225 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
226 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
227 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
229 /* controller 4, Base address 203000 */
230 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
231 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
232 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
233 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
234 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
235 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
238 #define CONFIG_PCI_INDIRECT_BRIDGE
240 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
241 #endif /* CONFIG_PCI */
244 #ifdef CONFIG_FSL_SATA_V2
245 #define CONFIG_LIBATA
246 #define CONFIG_FSL_SATA
248 #define CONFIG_SYS_SATA_MAX_DEVICE 2
250 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
251 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
253 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
254 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
259 #ifdef CONFIG_FMAN_ENET
260 #define CONFIG_MII /* MII PHY management */
261 #define CONFIG_ETHPRIME "FM1@DTSEC1"
262 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
268 #define CONFIG_LOADS_ECHO /* echo on for serial download */
269 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
272 * Command line configuration.
276 #define CONFIG_CMD_PCI
280 * Miscellaneous configurable options
282 #define CONFIG_SYS_LONGHELP /* undef to save memory */
283 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
284 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
285 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
286 #ifdef CONFIG_CMD_KGDB
287 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
289 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
291 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
292 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
293 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
296 * For booting Linux, the board info and command line data
297 * have to be in the first 64 MB of memory, since this is
298 * the maximum mapped by the Linux kernel during initialization.
300 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
301 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
303 #ifdef CONFIG_CMD_KGDB
304 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
308 * Environment Configuration
310 #define CONFIG_ROOTPATH "/opt/nfsroot"
311 #define CONFIG_BOOTFILE "uImage"
312 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
314 /* default location for tftp and bootm */
315 #define CONFIG_LOADADDR 1000000
317 #define CONFIG_HVBOOT \
318 "setenv bootargs config-addr=0x60000000; " \
319 "bootm 0x01000000 - 0x00f00000"
321 #ifndef CONFIG_MTD_NOR_FLASH
323 #define CONFIG_FLASH_CFI_DRIVER
324 #define CONFIG_SYS_FLASH_CFI
325 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
328 #if defined(CONFIG_SPIFLASH)
329 #define CONFIG_SYS_EXTRA_ENV_RELOC
330 #define CONFIG_ENV_SPI_BUS 0
331 #define CONFIG_ENV_SPI_CS 0
332 #define CONFIG_ENV_SPI_MAX_HZ 10000000
333 #define CONFIG_ENV_SPI_MODE 0
334 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
335 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
336 #define CONFIG_ENV_SECT_SIZE 0x10000
337 #elif defined(CONFIG_SDCARD)
338 #define CONFIG_SYS_EXTRA_ENV_RELOC
339 #define CONFIG_SYS_MMC_ENV_DEV 0
340 #define CONFIG_ENV_SIZE 0x2000
341 #define CONFIG_ENV_OFFSET (512 * 0x800)
342 #elif defined(CONFIG_NAND)
343 #define CONFIG_SYS_EXTRA_ENV_RELOC
344 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
345 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
346 #elif defined(CONFIG_ENV_IS_NOWHERE)
347 #define CONFIG_ENV_SIZE 0x2000
349 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
350 #define CONFIG_ENV_SIZE 0x2000
351 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
354 #define CONFIG_SYS_CLK_FREQ 66666666
355 #define CONFIG_DDR_CLK_FREQ 133333333
358 unsigned long get_board_sys_clk(void);
359 unsigned long get_board_ddr_clk(void);
365 #define CONFIG_SYS_SPD_BUS_NUM 0
366 #define SPD_EEPROM_ADDRESS1 0x52
367 #define SPD_EEPROM_ADDRESS2 0x54
368 #define SPD_EEPROM_ADDRESS3 0x56
369 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
370 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
375 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
376 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
378 CSPR_PORT_SIZE_16 | \
381 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
382 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
383 CSPR_PORT_SIZE_16 | \
386 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
387 /* NOR Flash Timing Params */
388 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
390 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
391 FTIM0_NOR_TEADC(0x5) | \
392 FTIM0_NOR_TEAHC(0x5))
393 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
394 FTIM1_NOR_TRAD_NOR(0x1A) |\
395 FTIM1_NOR_TSEQRAD_NOR(0x13))
396 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
397 FTIM2_NOR_TCH(0x4) | \
398 FTIM2_NOR_TWPH(0x0E) | \
400 #define CONFIG_SYS_NOR_FTIM3 0x0
402 #define CONFIG_SYS_FLASH_QUIET_TEST
403 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
405 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
406 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
407 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
408 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
410 #define CONFIG_SYS_FLASH_EMPTY_INFO
411 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
412 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
414 /* NAND Flash on IFC */
415 #define CONFIG_NAND_FSL_IFC
416 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
417 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
418 #define CONFIG_SYS_NAND_BASE 0xff800000
419 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
421 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
422 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
423 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
424 | CSPR_MSEL_NAND /* MSEL = NAND */ \
426 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
428 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
429 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
430 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
431 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
432 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
433 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
434 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
436 #define CONFIG_SYS_NAND_ONFI_DETECTION
438 /* ONFI NAND Flash mode0 Timing Params */
439 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
440 FTIM0_NAND_TWP(0x18) | \
441 FTIM0_NAND_TWCHT(0x07) | \
442 FTIM0_NAND_TWH(0x0a))
443 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
444 FTIM1_NAND_TWBE(0x39) | \
445 FTIM1_NAND_TRR(0x0e) | \
446 FTIM1_NAND_TRP(0x18))
447 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
448 FTIM2_NAND_TREH(0x0a) | \
449 FTIM2_NAND_TWHRE(0x1e))
450 #define CONFIG_SYS_NAND_FTIM3 0x0
452 #define CONFIG_SYS_NAND_DDR_LAW 11
453 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
454 #define CONFIG_SYS_MAX_NAND_DEVICE 1
455 #define CONFIG_CMD_NAND
457 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
459 #if defined(CONFIG_NAND)
460 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
461 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
462 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
463 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
464 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
465 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
466 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
467 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
468 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
469 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
470 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
471 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
472 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
473 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
474 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
475 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
477 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
478 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
479 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
480 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
481 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
482 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
483 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
484 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
485 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
486 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
487 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
488 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
489 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
490 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
491 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
492 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
494 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
495 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
496 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
497 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
498 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
499 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
500 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
501 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
504 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
505 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
506 #define CONFIG_SYS_CSPR3_EXT (0xf)
507 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
512 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
513 #define CONFIG_SYS_CSOR3 0x0
515 /* CPLD Timing parameters for IFC CS3 */
516 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
517 FTIM0_GPCM_TEADC(0x0e) | \
518 FTIM0_GPCM_TEAHC(0x0e))
519 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
520 FTIM1_GPCM_TRAD(0x1f))
521 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
522 FTIM2_GPCM_TCH(0x8) | \
523 FTIM2_GPCM_TWP(0x1f))
524 #define CONFIG_SYS_CS3_FTIM3 0x0
526 #if defined(CONFIG_RAMBOOT_PBL)
527 #define CONFIG_SYS_RAMBOOT
531 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
532 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
533 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
534 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
536 #define I2C_MUX_CH_DEFAULT 0x8
537 #define I2C_MUX_CH_VOL_MONITOR 0xa
538 #define I2C_MUX_CH_VSC3316_FS 0xc
539 #define I2C_MUX_CH_VSC3316_BS 0xd
541 /* Voltage monitor on channel 2*/
542 #define I2C_VOL_MONITOR_ADDR 0x40
543 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
544 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
545 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
547 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
548 #ifndef CONFIG_SPL_BUILD
551 #define CONFIG_VOL_MONITOR_IR36021_SET
552 #define CONFIG_VOL_MONITOR_IR36021_READ
553 /* The lowest and highest voltage allowed for T4240RDB */
554 #define VDD_MV_MIN 819
555 #define VDD_MV_MAX 1212
558 * eSPI - Enhanced SPI
560 #define CONFIG_SF_DEFAULT_SPEED 10000000
561 #define CONFIG_SF_DEFAULT_MODE 0
564 #ifndef CONFIG_NOBQFMAN
565 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
566 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
567 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
568 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
569 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
570 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
571 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
572 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
573 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
574 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
575 CONFIG_SYS_BMAN_CENA_SIZE)
576 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
577 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
578 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
579 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
580 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
581 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
582 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
583 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
584 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
585 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
586 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
587 CONFIG_SYS_QMAN_CENA_SIZE)
588 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
589 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
591 #define CONFIG_SYS_DPAA_FMAN
592 #define CONFIG_SYS_DPAA_PME
593 #define CONFIG_SYS_PMAN
594 #define CONFIG_SYS_DPAA_DCE
595 #define CONFIG_SYS_DPAA_RMAN
596 #define CONFIG_SYS_INTERLAKEN
598 /* Default address of microcode for the Linux Fman driver */
599 #if defined(CONFIG_SPIFLASH)
601 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
602 * env, so we got 0x110000.
604 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
605 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
606 #elif defined(CONFIG_SDCARD)
608 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
609 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
610 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
612 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
613 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
614 #elif defined(CONFIG_NAND)
615 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
616 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
618 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
619 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
621 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
622 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
623 #endif /* CONFIG_NOBQFMAN */
625 #ifdef CONFIG_SYS_DPAA_FMAN
626 #define CONFIG_FMAN_ENET
627 #define CONFIG_PHYLIB_10G
628 #define CONFIG_PHY_VITESSE
629 #define CONFIG_PHY_CORTINA
630 #define CONFIG_SYS_CORTINA_FW_IN_NOR
631 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
632 #define CONFIG_CORTINA_FW_LENGTH 0x40000
633 #define CONFIG_PHY_TERANETICS
634 #define SGMII_PHY_ADDR1 0x0
635 #define SGMII_PHY_ADDR2 0x1
636 #define SGMII_PHY_ADDR3 0x2
637 #define SGMII_PHY_ADDR4 0x3
638 #define SGMII_PHY_ADDR5 0x4
639 #define SGMII_PHY_ADDR6 0x5
640 #define SGMII_PHY_ADDR7 0x6
641 #define SGMII_PHY_ADDR8 0x7
642 #define FM1_10GEC1_PHY_ADDR 0x10
643 #define FM1_10GEC2_PHY_ADDR 0x11
644 #define FM2_10GEC1_PHY_ADDR 0x12
645 #define FM2_10GEC2_PHY_ADDR 0x13
646 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
647 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
648 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
649 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
653 #ifdef CONFIG_FSL_SATA_V2
654 #define CONFIG_LIBATA
655 #define CONFIG_FSL_SATA
657 #define CONFIG_SYS_SATA_MAX_DEVICE 2
659 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
660 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
662 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
663 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
668 #ifdef CONFIG_FMAN_ENET
669 #define CONFIG_MII /* MII PHY management */
670 #define CONFIG_ETHPRIME "FM1@DTSEC1"
671 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
677 #define CONFIG_USB_EHCI_FSL
678 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
679 #define CONFIG_HAS_FSL_DR_USB
682 #define CONFIG_FSL_ESDHC
683 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
684 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
685 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
689 #define __USB_PHY_TYPE utmi
692 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
693 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
694 * interleaving. It can be cacheline, page, bank, superbank.
695 * See doc/README.fsl-ddr for details.
697 #ifdef CONFIG_ARCH_T4240
698 #define CTRL_INTLV_PREFERED 3way_4KB
700 #define CTRL_INTLV_PREFERED cacheline
703 #define CONFIG_EXTRA_ENV_SETTINGS \
704 "hwconfig=fsl_ddr:" \
705 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
707 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
709 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
710 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
711 "tftpflash=tftpboot $loadaddr $uboot && " \
712 "protect off $ubootaddr +$filesize && " \
713 "erase $ubootaddr +$filesize && " \
714 "cp.b $loadaddr $ubootaddr $filesize && " \
715 "protect on $ubootaddr +$filesize && " \
716 "cmp.b $loadaddr $ubootaddr $filesize\0" \
717 "consoledev=ttyS0\0" \
718 "ramdiskaddr=2000000\0" \
719 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
720 "fdtaddr=1e00000\0" \
721 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
724 #define CONFIG_HVBOOT \
725 "setenv bootargs config-addr=0x60000000; " \
726 "bootm 0x01000000 - 0x00f00000"
728 #define CONFIG_LINUX \
729 "setenv bootargs root=/dev/ram rw " \
730 "console=$consoledev,$baudrate $othbootargs;" \
731 "setenv ramdiskaddr 0x02000000;" \
732 "setenv fdtaddr 0x00c00000;" \
733 "setenv loadaddr 0x1000000;" \
734 "bootm $loadaddr $ramdiskaddr $fdtaddr"
736 #define CONFIG_HDBOOT \
737 "setenv bootargs root=/dev/$bdev rw " \
738 "console=$consoledev,$baudrate $othbootargs;" \
739 "tftp $loadaddr $bootfile;" \
740 "tftp $fdtaddr $fdtfile;" \
741 "bootm $loadaddr - $fdtaddr"
743 #define CONFIG_NFSBOOTCOMMAND \
744 "setenv bootargs root=/dev/nfs rw " \
745 "nfsroot=$serverip:$rootpath " \
746 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
747 "console=$consoledev,$baudrate $othbootargs;" \
748 "tftp $loadaddr $bootfile;" \
749 "tftp $fdtaddr $fdtfile;" \
750 "bootm $loadaddr - $fdtaddr"
752 #define CONFIG_RAMBOOTCOMMAND \
753 "setenv bootargs root=/dev/ram rw " \
754 "console=$consoledev,$baudrate $othbootargs;" \
755 "tftp $ramdiskaddr $ramdiskfile;" \
756 "tftp $loadaddr $bootfile;" \
757 "tftp $fdtaddr $fdtfile;" \
758 "bootm $loadaddr $ramdiskaddr $fdtaddr"
760 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
762 #include <asm/fsl_secure_boot.h>
764 #endif /* __CONFIG_H */