2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 RDB board configuration file
13 #define CONFIG_FSL_SATA_V2
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
18 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26 #define CONFIG_SYS_TEXT_BASE 0x00201000
27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
28 #define CONFIG_SPL_PAD_TO 0x40000
29 #define CONFIG_SPL_MAX_SIZE 0x28000
30 #define RESET_VECTOR_OFFSET 0x27FFC
31 #define BOOT_PAGE_OFFSET 0x27000
34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
35 #define CONFIG_SPL_MMC_MINIMAL
36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
40 #ifndef CONFIG_SPL_BUILD
41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
45 #define CONFIG_SPL_MMC_BOOT
48 #ifdef CONFIG_SPL_BUILD
49 #define CONFIG_SPL_SKIP_RELOCATE
50 #define CONFIG_SPL_COMMON_INIT_DDR
51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
55 #endif /* CONFIG_RAMBOOT_PBL */
57 #define CONFIG_DDR_ECC
59 /* High Level Configuration Options */
60 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
61 #define CONFIG_MP /* support multiple processors */
63 #ifndef CONFIG_SYS_TEXT_BASE
64 #define CONFIG_SYS_TEXT_BASE 0xeff40000
67 #ifndef CONFIG_RESET_VECTOR_ADDRESS
68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
71 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
72 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
73 #define CONFIG_PCIE1 /* PCIE controller 1 */
74 #define CONFIG_PCIE2 /* PCIE controller 2 */
75 #define CONFIG_PCIE3 /* PCIE controller 3 */
76 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
77 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
79 #define CONFIG_ENV_OVERWRITE
82 * These can be toggled for performance analysis, otherwise use default.
84 #define CONFIG_SYS_CACHE_STASHING
85 #define CONFIG_BTB /* toggle branch predition */
87 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
88 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
91 #define CONFIG_ENABLE_36BIT_PHYS
93 #define CONFIG_ADDR_MAP
94 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
96 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
97 #define CONFIG_SYS_MEMTEST_END 0x00400000
98 #define CONFIG_SYS_ALT_MEMTEST
99 #define CONFIG_PANIC_HANG /* do not reset board on panic */
102 * Config the L3 Cache as L3 SRAM
104 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
105 #define CONFIG_SYS_L3_SIZE (512 << 10)
106 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
107 #ifdef CONFIG_RAMBOOT_PBL
108 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
110 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
111 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
112 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
113 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
115 #define CONFIG_SYS_DCSRBAR 0xf0000000
116 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
121 #define CONFIG_VERY_BIG_RAM
122 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
125 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
126 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
127 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
129 #define CONFIG_DDR_SPD
134 #define CONFIG_SYS_FLASH_BASE 0xe0000000
135 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
137 #ifdef CONFIG_SPL_BUILD
138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
140 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
143 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
144 #define CONFIG_MISC_INIT_R
146 #define CONFIG_HWCONFIG
148 /* define to use L1 as initial stack */
149 #define CONFIG_L1_INIT_RAM
150 #define CONFIG_SYS_INIT_RAM_LOCK
151 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
152 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
153 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
154 /* The assembler doesn't like typecast */
155 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
156 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
157 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
158 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
160 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
161 GENERATED_GBL_DATA_SIZE)
162 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
164 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
165 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
167 /* Serial Port - controlled on board with jumper J8
171 #define CONFIG_CONS_INDEX 1
172 #define CONFIG_SYS_NS16550_SERIAL
173 #define CONFIG_SYS_NS16550_REG_SIZE 1
174 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
176 #define CONFIG_SYS_BAUDRATE_TABLE \
177 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
179 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
180 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
181 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
182 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
185 #define CONFIG_SYS_I2C
186 #define CONFIG_SYS_I2C_FSL
187 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
188 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
189 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
190 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
194 * Memory space is mapped 1-1, but I/O space must start from 0.
197 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
198 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
199 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
200 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
201 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
202 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
203 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
204 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
205 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
207 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
208 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
209 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
210 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
211 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
212 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
213 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
214 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
215 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
217 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
218 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
219 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
220 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
221 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
222 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
223 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
224 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
225 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
227 /* controller 4, Base address 203000 */
228 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
229 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
230 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
231 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
232 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
233 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
236 #define CONFIG_PCI_INDIRECT_BRIDGE
238 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
239 #endif /* CONFIG_PCI */
242 #ifdef CONFIG_FSL_SATA_V2
243 #define CONFIG_SYS_SATA_MAX_DEVICE 2
245 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
246 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
248 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
249 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
254 #ifdef CONFIG_FMAN_ENET
255 #define CONFIG_MII /* MII PHY management */
256 #define CONFIG_ETHPRIME "FM1@DTSEC1"
262 #define CONFIG_LOADS_ECHO /* echo on for serial download */
263 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
266 * Command line configuration.
270 * Miscellaneous configurable options
272 #define CONFIG_SYS_LONGHELP /* undef to save memory */
273 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
274 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
275 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
278 * For booting Linux, the board info and command line data
279 * have to be in the first 64 MB of memory, since this is
280 * the maximum mapped by the Linux kernel during initialization.
282 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
283 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
285 #ifdef CONFIG_CMD_KGDB
286 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
290 * Environment Configuration
292 #define CONFIG_ROOTPATH "/opt/nfsroot"
293 #define CONFIG_BOOTFILE "uImage"
294 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
296 /* default location for tftp and bootm */
297 #define CONFIG_LOADADDR 1000000
299 #define CONFIG_HVBOOT \
300 "setenv bootargs config-addr=0x60000000; " \
301 "bootm 0x01000000 - 0x00f00000"
303 #ifndef CONFIG_MTD_NOR_FLASH
305 #define CONFIG_FLASH_CFI_DRIVER
306 #define CONFIG_SYS_FLASH_CFI
307 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
310 #if defined(CONFIG_SPIFLASH)
311 #define CONFIG_SYS_EXTRA_ENV_RELOC
312 #define CONFIG_ENV_SPI_BUS 0
313 #define CONFIG_ENV_SPI_CS 0
314 #define CONFIG_ENV_SPI_MAX_HZ 10000000
315 #define CONFIG_ENV_SPI_MODE 0
316 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
317 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
318 #define CONFIG_ENV_SECT_SIZE 0x10000
319 #elif defined(CONFIG_SDCARD)
320 #define CONFIG_SYS_EXTRA_ENV_RELOC
321 #define CONFIG_SYS_MMC_ENV_DEV 0
322 #define CONFIG_ENV_SIZE 0x2000
323 #define CONFIG_ENV_OFFSET (512 * 0x800)
324 #elif defined(CONFIG_NAND)
325 #define CONFIG_SYS_EXTRA_ENV_RELOC
326 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
327 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
328 #elif defined(CONFIG_ENV_IS_NOWHERE)
329 #define CONFIG_ENV_SIZE 0x2000
331 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
332 #define CONFIG_ENV_SIZE 0x2000
333 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
336 #define CONFIG_SYS_CLK_FREQ 66666666
337 #define CONFIG_DDR_CLK_FREQ 133333333
340 unsigned long get_board_sys_clk(void);
341 unsigned long get_board_ddr_clk(void);
347 #define CONFIG_SYS_SPD_BUS_NUM 0
348 #define SPD_EEPROM_ADDRESS1 0x52
349 #define SPD_EEPROM_ADDRESS2 0x54
350 #define SPD_EEPROM_ADDRESS3 0x56
351 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
352 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
357 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
358 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
360 CSPR_PORT_SIZE_16 | \
363 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
364 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
365 CSPR_PORT_SIZE_16 | \
368 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
369 /* NOR Flash Timing Params */
370 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
372 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
373 FTIM0_NOR_TEADC(0x5) | \
374 FTIM0_NOR_TEAHC(0x5))
375 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
376 FTIM1_NOR_TRAD_NOR(0x1A) |\
377 FTIM1_NOR_TSEQRAD_NOR(0x13))
378 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
379 FTIM2_NOR_TCH(0x4) | \
380 FTIM2_NOR_TWPH(0x0E) | \
382 #define CONFIG_SYS_NOR_FTIM3 0x0
384 #define CONFIG_SYS_FLASH_QUIET_TEST
385 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
387 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
388 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
389 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
390 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
392 #define CONFIG_SYS_FLASH_EMPTY_INFO
393 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
394 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
396 /* NAND Flash on IFC */
397 #define CONFIG_NAND_FSL_IFC
398 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
399 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
400 #define CONFIG_SYS_NAND_BASE 0xff800000
401 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
403 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
404 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
405 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
406 | CSPR_MSEL_NAND /* MSEL = NAND */ \
408 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
410 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
411 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
412 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
413 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
414 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
415 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
416 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
418 #define CONFIG_SYS_NAND_ONFI_DETECTION
420 /* ONFI NAND Flash mode0 Timing Params */
421 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
422 FTIM0_NAND_TWP(0x18) | \
423 FTIM0_NAND_TWCHT(0x07) | \
424 FTIM0_NAND_TWH(0x0a))
425 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
426 FTIM1_NAND_TWBE(0x39) | \
427 FTIM1_NAND_TRR(0x0e) | \
428 FTIM1_NAND_TRP(0x18))
429 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
430 FTIM2_NAND_TREH(0x0a) | \
431 FTIM2_NAND_TWHRE(0x1e))
432 #define CONFIG_SYS_NAND_FTIM3 0x0
434 #define CONFIG_SYS_NAND_DDR_LAW 11
435 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
436 #define CONFIG_SYS_MAX_NAND_DEVICE 1
438 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
440 #if defined(CONFIG_NAND)
441 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
442 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
443 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
444 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
445 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
446 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
447 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
448 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
449 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
450 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
451 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
452 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
453 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
454 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
455 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
456 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
458 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
459 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
460 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
461 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
462 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
463 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
464 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
465 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
466 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
467 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
468 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
469 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
470 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
471 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
472 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
473 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
475 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
476 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
477 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
478 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
479 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
480 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
481 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
482 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
485 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
486 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
487 #define CONFIG_SYS_CSPR3_EXT (0xf)
488 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
493 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
494 #define CONFIG_SYS_CSOR3 0x0
496 /* CPLD Timing parameters for IFC CS3 */
497 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
498 FTIM0_GPCM_TEADC(0x0e) | \
499 FTIM0_GPCM_TEAHC(0x0e))
500 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
501 FTIM1_GPCM_TRAD(0x1f))
502 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
503 FTIM2_GPCM_TCH(0x8) | \
504 FTIM2_GPCM_TWP(0x1f))
505 #define CONFIG_SYS_CS3_FTIM3 0x0
507 #if defined(CONFIG_RAMBOOT_PBL)
508 #define CONFIG_SYS_RAMBOOT
512 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
513 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
514 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
515 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
517 #define I2C_MUX_CH_DEFAULT 0x8
518 #define I2C_MUX_CH_VOL_MONITOR 0xa
519 #define I2C_MUX_CH_VSC3316_FS 0xc
520 #define I2C_MUX_CH_VSC3316_BS 0xd
522 /* Voltage monitor on channel 2*/
523 #define I2C_VOL_MONITOR_ADDR 0x40
524 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
525 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
526 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
528 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
529 #ifndef CONFIG_SPL_BUILD
532 #define CONFIG_VOL_MONITOR_IR36021_SET
533 #define CONFIG_VOL_MONITOR_IR36021_READ
534 /* The lowest and highest voltage allowed for T4240RDB */
535 #define VDD_MV_MIN 819
536 #define VDD_MV_MAX 1212
539 * eSPI - Enhanced SPI
541 #define CONFIG_SF_DEFAULT_SPEED 10000000
542 #define CONFIG_SF_DEFAULT_MODE 0
545 #ifndef CONFIG_NOBQFMAN
546 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
547 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
548 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
549 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
550 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
551 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
552 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
553 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
554 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
555 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
556 CONFIG_SYS_BMAN_CENA_SIZE)
557 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
558 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
559 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
560 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
561 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
562 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
563 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
564 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
565 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
566 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
567 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
568 CONFIG_SYS_QMAN_CENA_SIZE)
569 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
570 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
572 #define CONFIG_SYS_DPAA_FMAN
573 #define CONFIG_SYS_DPAA_PME
574 #define CONFIG_SYS_PMAN
575 #define CONFIG_SYS_DPAA_DCE
576 #define CONFIG_SYS_DPAA_RMAN
577 #define CONFIG_SYS_INTERLAKEN
579 /* Default address of microcode for the Linux Fman driver */
580 #if defined(CONFIG_SPIFLASH)
582 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
583 * env, so we got 0x110000.
585 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
586 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
587 #elif defined(CONFIG_SDCARD)
589 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
590 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
591 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
593 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
594 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
595 #elif defined(CONFIG_NAND)
596 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
597 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
599 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
600 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
602 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
603 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
604 #endif /* CONFIG_NOBQFMAN */
606 #ifdef CONFIG_SYS_DPAA_FMAN
607 #define CONFIG_FMAN_ENET
608 #define CONFIG_PHYLIB_10G
609 #define CONFIG_PHY_VITESSE
610 #define CONFIG_PHY_CORTINA
611 #define CONFIG_SYS_CORTINA_FW_IN_NOR
612 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
613 #define CONFIG_CORTINA_FW_LENGTH 0x40000
614 #define CONFIG_PHY_TERANETICS
615 #define SGMII_PHY_ADDR1 0x0
616 #define SGMII_PHY_ADDR2 0x1
617 #define SGMII_PHY_ADDR3 0x2
618 #define SGMII_PHY_ADDR4 0x3
619 #define SGMII_PHY_ADDR5 0x4
620 #define SGMII_PHY_ADDR6 0x5
621 #define SGMII_PHY_ADDR7 0x6
622 #define SGMII_PHY_ADDR8 0x7
623 #define FM1_10GEC1_PHY_ADDR 0x10
624 #define FM1_10GEC2_PHY_ADDR 0x11
625 #define FM2_10GEC1_PHY_ADDR 0x12
626 #define FM2_10GEC2_PHY_ADDR 0x13
627 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
628 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
629 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
630 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
634 #ifdef CONFIG_FSL_SATA_V2
635 #define CONFIG_SYS_SATA_MAX_DEVICE 2
637 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
638 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
640 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
641 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
646 #ifdef CONFIG_FMAN_ENET
647 #define CONFIG_MII /* MII PHY management */
648 #define CONFIG_ETHPRIME "FM1@DTSEC1"
654 #define CONFIG_USB_EHCI_FSL
655 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
656 #define CONFIG_HAS_FSL_DR_USB
659 #define CONFIG_FSL_ESDHC
660 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
661 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
662 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
666 #define __USB_PHY_TYPE utmi
669 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
670 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
671 * interleaving. It can be cacheline, page, bank, superbank.
672 * See doc/README.fsl-ddr for details.
674 #ifdef CONFIG_ARCH_T4240
675 #define CTRL_INTLV_PREFERED 3way_4KB
677 #define CTRL_INTLV_PREFERED cacheline
680 #define CONFIG_EXTRA_ENV_SETTINGS \
681 "hwconfig=fsl_ddr:" \
682 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
684 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
686 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
687 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
688 "tftpflash=tftpboot $loadaddr $uboot && " \
689 "protect off $ubootaddr +$filesize && " \
690 "erase $ubootaddr +$filesize && " \
691 "cp.b $loadaddr $ubootaddr $filesize && " \
692 "protect on $ubootaddr +$filesize && " \
693 "cmp.b $loadaddr $ubootaddr $filesize\0" \
694 "consoledev=ttyS0\0" \
695 "ramdiskaddr=2000000\0" \
696 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
697 "fdtaddr=1e00000\0" \
698 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
701 #define CONFIG_HVBOOT \
702 "setenv bootargs config-addr=0x60000000; " \
703 "bootm 0x01000000 - 0x00f00000"
705 #define CONFIG_LINUX \
706 "setenv bootargs root=/dev/ram rw " \
707 "console=$consoledev,$baudrate $othbootargs;" \
708 "setenv ramdiskaddr 0x02000000;" \
709 "setenv fdtaddr 0x00c00000;" \
710 "setenv loadaddr 0x1000000;" \
711 "bootm $loadaddr $ramdiskaddr $fdtaddr"
713 #define CONFIG_HDBOOT \
714 "setenv bootargs root=/dev/$bdev rw " \
715 "console=$consoledev,$baudrate $othbootargs;" \
716 "tftp $loadaddr $bootfile;" \
717 "tftp $fdtaddr $fdtfile;" \
718 "bootm $loadaddr - $fdtaddr"
720 #define CONFIG_NFSBOOTCOMMAND \
721 "setenv bootargs root=/dev/nfs rw " \
722 "nfsroot=$serverip:$rootpath " \
723 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
724 "console=$consoledev,$baudrate $othbootargs;" \
725 "tftp $loadaddr $bootfile;" \
726 "tftp $fdtaddr $fdtfile;" \
727 "bootm $loadaddr - $fdtaddr"
729 #define CONFIG_RAMBOOTCOMMAND \
730 "setenv bootargs root=/dev/ram rw " \
731 "console=$consoledev,$baudrate $othbootargs;" \
732 "tftp $ramdiskaddr $ramdiskfile;" \
733 "tftp $loadaddr $bootfile;" \
734 "tftp $fdtaddr $fdtfile;" \
735 "bootm $loadaddr $ramdiskaddr $fdtaddr"
737 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
739 #include <asm/fsl_secure_boot.h>
741 #endif /* __CONFIG_H */