git.sur5r.net Git - u-boot/blob - include/configs/T4240RDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_FSL_SATA_V2
  14 #define CONFIG_PCIE4
  15
  16 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  17
  18 #ifdef CONFIG_RAMBOOT_PBL
  19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  20 #ifndef CONFIG_SDCARD
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define CONFIG_SPL_FLUSH_IMAGE
  25 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  26 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  27 #define CONFIG_SPL_PAD_TO               0x40000
  28 #define CONFIG_SPL_MAX_SIZE             0x28000
  29 #define RESET_VECTOR_OFFSET             0x27FFC
  30 #define BOOT_PAGE_OFFSET                0x27000
  31
  32 #ifdef  CONFIG_SDCARD
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  34 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  35 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  36 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  37 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  38 #ifndef CONFIG_SPL_BUILD
  39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  40 #endif
  41 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  42 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  43 #define CONFIG_SPL_MMC_BOOT
  44 #endif
  45
  46 #ifdef CONFIG_SPL_BUILD
  47 #define CONFIG_SPL_SKIP_RELOCATE
  48 #define CONFIG_SPL_COMMON_INIT_DDR
  49 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  50 #endif
  51
  52 #endif
  53 #endif /* CONFIG_RAMBOOT_PBL */
  54
  55 #define CONFIG_DDR_ECC
  56
  57 /* High Level Configuration Options */
  58 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  59 #define CONFIG_MP                       /* support multiple processors */
  60
  61 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  62 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  63 #endif
  64
  65 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  66 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  67 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  68 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  69 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  70 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  71 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  72
  73 #define CONFIG_ENV_OVERWRITE
  74
  75 /*
  76  * These can be toggled for performance analysis, otherwise use default.
  77  */
  78 #define CONFIG_SYS_CACHE_STASHING
  79 #define CONFIG_BTB                      /* toggle branch predition */
  80 #ifdef CONFIG_DDR_ECC
  81 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  82 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  83 #endif
  84
  85 #define CONFIG_ENABLE_36BIT_PHYS
  86
  87 #define CONFIG_ADDR_MAP
  88 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  89
  90 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  91 #define CONFIG_SYS_MEMTEST_END          0x00400000
  92 #define CONFIG_SYS_ALT_MEMTEST
  93
  94 /*
  95  *  Config the L3 Cache as L3 SRAM
  96  */
  97 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  98 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  99 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 100 #ifdef CONFIG_RAMBOOT_PBL
 101 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 102 #endif
 103 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 104 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 105 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 106 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 107
 108 #define CONFIG_SYS_DCSRBAR              0xf0000000
 109 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 110
 111 /*
 112  * DDR Setup
 113  */
 114 #define CONFIG_VERY_BIG_RAM
 115 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 116 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 117
 118 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 119 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 120 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 121
 122 #define CONFIG_DDR_SPD
 123
 124 /*
 125  * IFC Definitions
 126  */
 127 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 128 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 129
 130 #ifdef CONFIG_SPL_BUILD
 131 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 132 #else
 133 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 134 #endif
 135
 136 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 137 #define CONFIG_MISC_INIT_R
 138
 139 #define CONFIG_HWCONFIG
 140
 141 /* define to use L1 as initial stack */
 142 #define CONFIG_L1_INIT_RAM
 143 #define CONFIG_SYS_INIT_RAM_LOCK
 144 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 145 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 146 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 147 /* The assembler doesn't like typecast */
 148 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 149         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 150           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 151 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 152
 153 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 154                                         GENERATED_GBL_DATA_SIZE)
 155 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 156
 157 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 158 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 159
 160 /* Serial Port - controlled on board with jumper J8
 161  * open - index 2
 162  * shorted - index 1
 163  */
 164 #define CONFIG_CONS_INDEX       1
 165 #define CONFIG_SYS_NS16550_SERIAL
 166 #define CONFIG_SYS_NS16550_REG_SIZE     1
 167 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 168
 169 #define CONFIG_SYS_BAUDRATE_TABLE       \
 170         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 171
 172 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 173 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 174 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 175 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 176
 177 /* I2C */
 178 #define CONFIG_SYS_I2C
 179 #define CONFIG_SYS_I2C_FSL
 180 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 181 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 182 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 183 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 184
 185 /*
 186  * General PCI
 187  * Memory space is mapped 1-1, but I/O space must start from 0.
 188  */
 189
 190 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 191 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 192 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 193 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 194 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 195 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 196 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 197 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 198 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 199
 200 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 201 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 202 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 203 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 204 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 205 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 206 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 207 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 208 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 209
 210 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 211 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 212 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 213 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 214 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 215 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 216 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 217 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 218 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 219
 220 /* controller 4, Base address 203000 */
 221 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 222 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 223 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 224 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 225 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 226 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 227
 228 #ifdef CONFIG_PCI
 229 #define CONFIG_PCI_INDIRECT_BRIDGE
 230
 231 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 232 #endif  /* CONFIG_PCI */
 233
 234 /* SATA */
 235 #ifdef CONFIG_FSL_SATA_V2
 236 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 237 #define CONFIG_SATA1
 238 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 239 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 240 #define CONFIG_SATA2
 241 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 242 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 243
 244 #define CONFIG_LBA48
 245 #endif
 246
 247 #ifdef CONFIG_FMAN_ENET
 248 #define CONFIG_MII              /* MII PHY management */
 249 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 250 #endif
 251
 252 /*
 253  * Environment
 254  */
 255 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 256 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 257
 258 /*
 259  * Command line configuration.
 260  */
 261
 262 /*
 263  * Miscellaneous configurable options
 264  */
 265 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 266
 267 /*
 268  * For booting Linux, the board info and command line data
 269  * have to be in the first 64 MB of memory, since this is
 270  * the maximum mapped by the Linux kernel during initialization.
 271  */
 272 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 273 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 274
 275 #ifdef CONFIG_CMD_KGDB
 276 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 277 #endif
 278
 279 /*
 280  * Environment Configuration
 281  */
 282 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 283 #define CONFIG_BOOTFILE         "uImage"
 284 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 285
 286 /* default location for tftp and bootm */
 287 #define CONFIG_LOADADDR         1000000
 288
 289 #define CONFIG_HVBOOT                                   \
 290         "setenv bootargs config-addr=0x60000000; "      \
 291         "bootm 0x01000000 - 0x00f00000"
 292
 293 #ifndef CONFIG_MTD_NOR_FLASH
 294 #else
 295 #define CONFIG_FLASH_CFI_DRIVER
 296 #define CONFIG_SYS_FLASH_CFI
 297 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 298 #endif
 299
 300 #if defined(CONFIG_SPIFLASH)
 301 #define CONFIG_SYS_EXTRA_ENV_RELOC
 302 #define CONFIG_ENV_SPI_BUS              0
 303 #define CONFIG_ENV_SPI_CS               0
 304 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 305 #define CONFIG_ENV_SPI_MODE             0
 306 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 307 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 308 #define CONFIG_ENV_SECT_SIZE            0x10000
 309 #elif defined(CONFIG_SDCARD)
 310 #define CONFIG_SYS_EXTRA_ENV_RELOC
 311 #define CONFIG_SYS_MMC_ENV_DEV          0
 312 #define CONFIG_ENV_SIZE                 0x2000
 313 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 314 #elif defined(CONFIG_NAND)
 315 #define CONFIG_SYS_EXTRA_ENV_RELOC
 316 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 317 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 318 #elif defined(CONFIG_ENV_IS_NOWHERE)
 319 #define CONFIG_ENV_SIZE         0x2000
 320 #else
 321 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 322 #define CONFIG_ENV_SIZE         0x2000
 323 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 324 #endif
 325
 326 #define CONFIG_SYS_CLK_FREQ     66666666
 327 #define CONFIG_DDR_CLK_FREQ     133333333
 328
 329 #ifndef __ASSEMBLY__
 330 unsigned long get_board_sys_clk(void);
 331 unsigned long get_board_ddr_clk(void);
 332 #endif
 333
 334 /*
 335  * DDR Setup
 336  */
 337 #define CONFIG_SYS_SPD_BUS_NUM  0
 338 #define SPD_EEPROM_ADDRESS1     0x52
 339 #define SPD_EEPROM_ADDRESS2     0x54
 340 #define SPD_EEPROM_ADDRESS3     0x56
 341 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 342 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 343
 344 /*
 345  * IFC Definitions
 346  */
 347 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 348 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 349                                 + 0x8000000) | \
 350                                 CSPR_PORT_SIZE_16 | \
 351                                 CSPR_MSEL_NOR | \
 352                                 CSPR_V)
 353 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 354 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 355                                 CSPR_PORT_SIZE_16 | \
 356                                 CSPR_MSEL_NOR | \
 357                                 CSPR_V)
 358 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 359 /* NOR Flash Timing Params */
 360 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 361
 362 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 363                                 FTIM0_NOR_TEADC(0x5) | \
 364                                 FTIM0_NOR_TEAHC(0x5))
 365 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 366                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 367                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 368 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 369                                 FTIM2_NOR_TCH(0x4) | \
 370                                 FTIM2_NOR_TWPH(0x0E) | \
 371                                 FTIM2_NOR_TWP(0x1c))
 372 #define CONFIG_SYS_NOR_FTIM3    0x0
 373
 374 #define CONFIG_SYS_FLASH_QUIET_TEST
 375 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 376
 377 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 378 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 379 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 380 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 381
 382 #define CONFIG_SYS_FLASH_EMPTY_INFO
 383 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 384                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 385
 386 /* NAND Flash on IFC */
 387 #define CONFIG_NAND_FSL_IFC
 388 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 389 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 390 #define CONFIG_SYS_NAND_BASE            0xff800000
 391 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 392
 393 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 394 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 395                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 396                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 397                                 | CSPR_V)
 398 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 399
 400 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 401                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 402                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 403                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 404                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 405                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 406                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 407
 408 #define CONFIG_SYS_NAND_ONFI_DETECTION
 409
 410 /* ONFI NAND Flash mode0 Timing Params */
 411 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 412                                         FTIM0_NAND_TWP(0x18)   | \
 413                                         FTIM0_NAND_TWCHT(0x07) | \
 414                                         FTIM0_NAND_TWH(0x0a))
 415 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 416                                         FTIM1_NAND_TWBE(0x39)  | \
 417                                         FTIM1_NAND_TRR(0x0e)   | \
 418                                         FTIM1_NAND_TRP(0x18))
 419 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 420                                         FTIM2_NAND_TREH(0x0a) | \
 421                                         FTIM2_NAND_TWHRE(0x1e))
 422 #define CONFIG_SYS_NAND_FTIM3           0x0
 423
 424 #define CONFIG_SYS_NAND_DDR_LAW         11
 425 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 426 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 427
 428 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 429
 430 #if defined(CONFIG_NAND)
 431 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 432 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 433 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 434 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 435 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 436 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 437 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 438 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 439 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 440 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 441 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 442 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 443 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 444 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 445 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 446 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 447 #else
 448 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 449 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 450 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 451 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 452 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 453 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 454 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 455 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 456 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 457 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 458 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 459 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 460 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 461 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 462 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 463 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 464 #endif
 465 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 466 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 467 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 468 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 469 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 470 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 471 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 472 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 473
 474 /* CPLD on IFC */
 475 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 476 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 477 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 478 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 479                                 | CSPR_PORT_SIZE_8 \
 480                                 | CSPR_MSEL_GPCM \
 481                                 | CSPR_V)
 482
 483 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 484 #define CONFIG_SYS_CSOR3        0x0
 485
 486 /* CPLD Timing parameters for IFC CS3 */
 487 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 488                                         FTIM0_GPCM_TEADC(0x0e) | \
 489                                         FTIM0_GPCM_TEAHC(0x0e))
 490 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 491                                         FTIM1_GPCM_TRAD(0x1f))
 492 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 493                                         FTIM2_GPCM_TCH(0x8) | \
 494                                         FTIM2_GPCM_TWP(0x1f))
 495 #define CONFIG_SYS_CS3_FTIM3            0x0
 496
 497 #if defined(CONFIG_RAMBOOT_PBL)
 498 #define CONFIG_SYS_RAMBOOT
 499 #endif
 500
 501 /* I2C */
 502 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 503 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 504 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 505 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 506
 507 #define I2C_MUX_CH_DEFAULT      0x8
 508 #define I2C_MUX_CH_VOL_MONITOR  0xa
 509 #define I2C_MUX_CH_VSC3316_FS   0xc
 510 #define I2C_MUX_CH_VSC3316_BS   0xd
 511
 512 /* Voltage monitor on channel 2*/
 513 #define I2C_VOL_MONITOR_ADDR            0x40
 514 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 515 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 516 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 517
 518 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 519 #ifndef CONFIG_SPL_BUILD
 520 #define CONFIG_VID
 521 #endif
 522 #define CONFIG_VOL_MONITOR_IR36021_SET
 523 #define CONFIG_VOL_MONITOR_IR36021_READ
 524 /* The lowest and highest voltage allowed for T4240RDB */
 525 #define VDD_MV_MIN                      819
 526 #define VDD_MV_MAX                      1212
 527
 528 /*
 529  * eSPI - Enhanced SPI
 530  */
 531 #define CONFIG_SF_DEFAULT_SPEED         10000000
 532 #define CONFIG_SF_DEFAULT_MODE          0
 533
 534 /* Qman/Bman */
 535 #ifndef CONFIG_NOBQFMAN
 536 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 537 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 538 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 539 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 540 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 541 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 542 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 543 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 544 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 545                                         CONFIG_SYS_BMAN_CENA_SIZE)
 546 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 547 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 548 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 549 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 550 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 551 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 552 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 553 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 554 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 555 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 556 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 557                                         CONFIG_SYS_QMAN_CENA_SIZE)
 558 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 559 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 560
 561 #define CONFIG_SYS_DPAA_FMAN
 562 #define CONFIG_SYS_DPAA_PME
 563 #define CONFIG_SYS_PMAN
 564 #define CONFIG_SYS_DPAA_DCE
 565 #define CONFIG_SYS_DPAA_RMAN
 566 #define CONFIG_SYS_INTERLAKEN
 567
 568 /* Default address of microcode for the Linux Fman driver */
 569 #if defined(CONFIG_SPIFLASH)
 570 /*
 571  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 572  * env, so we got 0x110000.
 573  */
 574 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 575 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 576 #elif defined(CONFIG_SDCARD)
 577 /*
 578  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 579  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 580  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 581  */
 582 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 583 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 584 #elif defined(CONFIG_NAND)
 585 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 586 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 587 #else
 588 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 589 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 590 #endif
 591 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 592 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 593 #endif /* CONFIG_NOBQFMAN */
 594
 595 #ifdef CONFIG_SYS_DPAA_FMAN
 596 #define CONFIG_FMAN_ENET
 597 #define CONFIG_PHYLIB_10G
 598 #define CONFIG_PHY_VITESSE
 599 #define CONFIG_PHY_CORTINA
 600 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 601 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
 602 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 603 #define CONFIG_PHY_TERANETICS
 604 #define SGMII_PHY_ADDR1 0x0
 605 #define SGMII_PHY_ADDR2 0x1
 606 #define SGMII_PHY_ADDR3 0x2
 607 #define SGMII_PHY_ADDR4 0x3
 608 #define SGMII_PHY_ADDR5 0x4
 609 #define SGMII_PHY_ADDR6 0x5
 610 #define SGMII_PHY_ADDR7 0x6
 611 #define SGMII_PHY_ADDR8 0x7
 612 #define FM1_10GEC1_PHY_ADDR     0x10
 613 #define FM1_10GEC2_PHY_ADDR     0x11
 614 #define FM2_10GEC1_PHY_ADDR     0x12
 615 #define FM2_10GEC2_PHY_ADDR     0x13
 616 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 617 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 618 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 619 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 620 #endif
 621
 622 /* SATA */
 623 #ifdef CONFIG_FSL_SATA_V2
 624 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 625 #define CONFIG_SATA1
 626 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 627 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 628 #define CONFIG_SATA2
 629 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 630 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 631
 632 #define CONFIG_LBA48
 633 #endif
 634
 635 #ifdef CONFIG_FMAN_ENET
 636 #define CONFIG_MII              /* MII PHY management */
 637 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 638 #endif
 639
 640 /*
 641 * USB
 642 */
 643 #define CONFIG_USB_EHCI_FSL
 644 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 645 #define CONFIG_HAS_FSL_DR_USB
 646
 647 #ifdef CONFIG_MMC
 648 #define CONFIG_FSL_ESDHC
 649 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 650 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 651 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 652 #endif
 653
 654
 655 #define __USB_PHY_TYPE  utmi
 656
 657 /*
 658  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 659  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 660  * interleaving. It can be cacheline, page, bank, superbank.
 661  * See doc/README.fsl-ddr for details.
 662  */
 663 #ifdef CONFIG_ARCH_T4240
 664 #define CTRL_INTLV_PREFERED 3way_4KB
 665 #else
 666 #define CTRL_INTLV_PREFERED cacheline
 667 #endif
 668
 669 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 670         "hwconfig=fsl_ddr:"                                     \
 671         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 672         "bank_intlv=auto;"                                      \
 673         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 674         "netdev=eth0\0"                                         \
 675         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 676         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 677         "tftpflash=tftpboot $loadaddr $uboot && "               \
 678         "protect off $ubootaddr +$filesize && "                 \
 679         "erase $ubootaddr +$filesize && "                       \
 680         "cp.b $loadaddr $ubootaddr $filesize && "               \
 681         "protect on $ubootaddr +$filesize && "                  \
 682         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 683         "consoledev=ttyS0\0"                                    \
 684         "ramdiskaddr=2000000\0"                                 \
 685         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 686         "fdtaddr=1e00000\0"                                     \
 687         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 688         "bdev=sda3\0"
 689
 690 #define CONFIG_HVBOOT                                   \
 691         "setenv bootargs config-addr=0x60000000; "      \
 692         "bootm 0x01000000 - 0x00f00000"
 693
 694 #define CONFIG_LINUX                                    \
 695         "setenv bootargs root=/dev/ram rw "             \
 696         "console=$consoledev,$baudrate $othbootargs;"   \
 697         "setenv ramdiskaddr 0x02000000;"                \
 698         "setenv fdtaddr 0x00c00000;"                    \
 699         "setenv loadaddr 0x1000000;"                    \
 700         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 701
 702 #define CONFIG_HDBOOT                                   \
 703         "setenv bootargs root=/dev/$bdev rw "           \
 704         "console=$consoledev,$baudrate $othbootargs;"   \
 705         "tftp $loadaddr $bootfile;"                     \
 706         "tftp $fdtaddr $fdtfile;"                       \
 707         "bootm $loadaddr - $fdtaddr"
 708
 709 #define CONFIG_NFSBOOTCOMMAND                   \
 710         "setenv bootargs root=/dev/nfs rw "     \
 711         "nfsroot=$serverip:$rootpath "          \
 712         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 713         "console=$consoledev,$baudrate $othbootargs;"   \
 714         "tftp $loadaddr $bootfile;"             \
 715         "tftp $fdtaddr $fdtfile;"               \
 716         "bootm $loadaddr - $fdtaddr"
 717
 718 #define CONFIG_RAMBOOTCOMMAND                           \
 719         "setenv bootargs root=/dev/ram rw "             \
 720         "console=$consoledev,$baudrate $othbootargs;"   \
 721         "tftp $ramdiskaddr $ramdiskfile;"               \
 722         "tftp $loadaddr $bootfile;"                     \
 723         "tftp $fdtaddr $fdtfile;"                       \
 724         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 725
 726 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 727
 728 #include <asm/fsl_secure_boot.h>
 729
 730 #endif  /* __CONFIG_H */