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[u-boot] / include / configs / T4240RDB.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * T4240 RDB board configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #define CONFIG_FSL_SATA_V2
14 #define CONFIG_PCIE4
15
16 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
17
18 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
20 #ifndef CONFIG_SDCARD
21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
23 #else
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
26 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
27 #define CONFIG_SPL_PAD_TO               0x40000
28 #define CONFIG_SPL_MAX_SIZE             0x28000
29 #define RESET_VECTOR_OFFSET             0x27FFC
30 #define BOOT_PAGE_OFFSET                0x27000
31
32 #ifdef  CONFIG_SDCARD
33 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
34 #define CONFIG_SPL_MMC_MINIMAL
35 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
36 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
37 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
38 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
39 #ifndef CONFIG_SPL_BUILD
40 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
41 #endif
42 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
43 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
44 #define CONFIG_SPL_MMC_BOOT
45 #endif
46
47 #ifdef CONFIG_SPL_BUILD
48 #define CONFIG_SPL_SKIP_RELOCATE
49 #define CONFIG_SPL_COMMON_INIT_DDR
50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
51 #endif
52
53 #endif
54 #endif /* CONFIG_RAMBOOT_PBL */
55
56 #define CONFIG_DDR_ECC
57
58 /* High Level Configuration Options */
59 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
60 #define CONFIG_MP                       /* support multiple processors */
61
62 #ifndef CONFIG_RESET_VECTOR_ADDRESS
63 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
64 #endif
65
66 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
67 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
68 #define CONFIG_PCIE1                    /* PCIE controller 1 */
69 #define CONFIG_PCIE2                    /* PCIE controller 2 */
70 #define CONFIG_PCIE3                    /* PCIE controller 3 */
71 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
72 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
73
74 #define CONFIG_ENV_OVERWRITE
75
76 /*
77  * These can be toggled for performance analysis, otherwise use default.
78  */
79 #define CONFIG_SYS_CACHE_STASHING
80 #define CONFIG_BTB                      /* toggle branch predition */
81 #ifdef CONFIG_DDR_ECC
82 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
83 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
84 #endif
85
86 #define CONFIG_ENABLE_36BIT_PHYS
87
88 #define CONFIG_ADDR_MAP
89 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
90
91 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
92 #define CONFIG_SYS_MEMTEST_END          0x00400000
93 #define CONFIG_SYS_ALT_MEMTEST
94
95 /*
96  *  Config the L3 Cache as L3 SRAM
97  */
98 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
99 #define CONFIG_SYS_L3_SIZE              (512 << 10)
100 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
101 #ifdef CONFIG_RAMBOOT_PBL
102 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
103 #endif
104 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
105 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
106 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
107 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
108
109 #define CONFIG_SYS_DCSRBAR              0xf0000000
110 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
111
112 /*
113  * DDR Setup
114  */
115 #define CONFIG_VERY_BIG_RAM
116 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
117 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
118
119 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
120 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
121 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
122
123 #define CONFIG_DDR_SPD
124
125 /*
126  * IFC Definitions
127  */
128 #define CONFIG_SYS_FLASH_BASE   0xe0000000
129 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
130
131 #ifdef CONFIG_SPL_BUILD
132 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
133 #else
134 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
135 #endif
136
137 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
138 #define CONFIG_MISC_INIT_R
139
140 #define CONFIG_HWCONFIG
141
142 /* define to use L1 as initial stack */
143 #define CONFIG_L1_INIT_RAM
144 #define CONFIG_SYS_INIT_RAM_LOCK
145 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
146 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
147 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
148 /* The assembler doesn't like typecast */
149 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
150         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
151           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
152 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
153
154 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
155                                         GENERATED_GBL_DATA_SIZE)
156 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
157
158 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
159 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
160
161 /* Serial Port - controlled on board with jumper J8
162  * open - index 2
163  * shorted - index 1
164  */
165 #define CONFIG_CONS_INDEX       1
166 #define CONFIG_SYS_NS16550_SERIAL
167 #define CONFIG_SYS_NS16550_REG_SIZE     1
168 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
169
170 #define CONFIG_SYS_BAUDRATE_TABLE       \
171         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
172
173 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
174 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
175 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
176 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
177
178 /* I2C */
179 #define CONFIG_SYS_I2C
180 #define CONFIG_SYS_I2C_FSL
181 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
182 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
183 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
184 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
185
186 /*
187  * General PCI
188  * Memory space is mapped 1-1, but I/O space must start from 0.
189  */
190
191 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
192 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
193 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
194 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
195 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
196 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
197 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
198 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
199 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
200
201 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
202 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
203 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
204 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
205 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
206 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
207 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
208 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
209 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
210
211 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
212 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
213 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
214 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
215 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
216 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
217 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
218 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
219 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
220
221 /* controller 4, Base address 203000 */
222 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
223 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
224 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
225 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
226 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
227 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
228
229 #ifdef CONFIG_PCI
230 #define CONFIG_PCI_INDIRECT_BRIDGE
231
232 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
233 #endif  /* CONFIG_PCI */
234
235 /* SATA */
236 #ifdef CONFIG_FSL_SATA_V2
237 #define CONFIG_SYS_SATA_MAX_DEVICE      2
238 #define CONFIG_SATA1
239 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
240 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
241 #define CONFIG_SATA2
242 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
243 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
244
245 #define CONFIG_LBA48
246 #endif
247
248 #ifdef CONFIG_FMAN_ENET
249 #define CONFIG_MII              /* MII PHY management */
250 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
251 #endif
252
253 /*
254  * Environment
255  */
256 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
257 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
258
259 /*
260  * Command line configuration.
261  */
262
263 /*
264  * Miscellaneous configurable options
265  */
266 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
267 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
268 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
269 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
270
271 /*
272  * For booting Linux, the board info and command line data
273  * have to be in the first 64 MB of memory, since this is
274  * the maximum mapped by the Linux kernel during initialization.
275  */
276 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
277 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
278
279 #ifdef CONFIG_CMD_KGDB
280 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
281 #endif
282
283 /*
284  * Environment Configuration
285  */
286 #define CONFIG_ROOTPATH         "/opt/nfsroot"
287 #define CONFIG_BOOTFILE         "uImage"
288 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
289
290 /* default location for tftp and bootm */
291 #define CONFIG_LOADADDR         1000000
292
293 #define CONFIG_HVBOOT                                   \
294         "setenv bootargs config-addr=0x60000000; "      \
295         "bootm 0x01000000 - 0x00f00000"
296
297 #ifndef CONFIG_MTD_NOR_FLASH
298 #else
299 #define CONFIG_FLASH_CFI_DRIVER
300 #define CONFIG_SYS_FLASH_CFI
301 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
302 #endif
303
304 #if defined(CONFIG_SPIFLASH)
305 #define CONFIG_SYS_EXTRA_ENV_RELOC
306 #define CONFIG_ENV_SPI_BUS              0
307 #define CONFIG_ENV_SPI_CS               0
308 #define CONFIG_ENV_SPI_MAX_HZ           10000000
309 #define CONFIG_ENV_SPI_MODE             0
310 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
311 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
312 #define CONFIG_ENV_SECT_SIZE            0x10000
313 #elif defined(CONFIG_SDCARD)
314 #define CONFIG_SYS_EXTRA_ENV_RELOC
315 #define CONFIG_SYS_MMC_ENV_DEV          0
316 #define CONFIG_ENV_SIZE                 0x2000
317 #define CONFIG_ENV_OFFSET               (512 * 0x800)
318 #elif defined(CONFIG_NAND)
319 #define CONFIG_SYS_EXTRA_ENV_RELOC
320 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
321 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
322 #elif defined(CONFIG_ENV_IS_NOWHERE)
323 #define CONFIG_ENV_SIZE         0x2000
324 #else
325 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
326 #define CONFIG_ENV_SIZE         0x2000
327 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
328 #endif
329
330 #define CONFIG_SYS_CLK_FREQ     66666666
331 #define CONFIG_DDR_CLK_FREQ     133333333
332
333 #ifndef __ASSEMBLY__
334 unsigned long get_board_sys_clk(void);
335 unsigned long get_board_ddr_clk(void);
336 #endif
337
338 /*
339  * DDR Setup
340  */
341 #define CONFIG_SYS_SPD_BUS_NUM  0
342 #define SPD_EEPROM_ADDRESS1     0x52
343 #define SPD_EEPROM_ADDRESS2     0x54
344 #define SPD_EEPROM_ADDRESS3     0x56
345 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
346 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
347
348 /*
349  * IFC Definitions
350  */
351 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
352 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
353                                 + 0x8000000) | \
354                                 CSPR_PORT_SIZE_16 | \
355                                 CSPR_MSEL_NOR | \
356                                 CSPR_V)
357 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
358 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
359                                 CSPR_PORT_SIZE_16 | \
360                                 CSPR_MSEL_NOR | \
361                                 CSPR_V)
362 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
363 /* NOR Flash Timing Params */
364 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
365
366 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
367                                 FTIM0_NOR_TEADC(0x5) | \
368                                 FTIM0_NOR_TEAHC(0x5))
369 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
370                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
371                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
372 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
373                                 FTIM2_NOR_TCH(0x4) | \
374                                 FTIM2_NOR_TWPH(0x0E) | \
375                                 FTIM2_NOR_TWP(0x1c))
376 #define CONFIG_SYS_NOR_FTIM3    0x0
377
378 #define CONFIG_SYS_FLASH_QUIET_TEST
379 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
380
381 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
382 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
383 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
384 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
385
386 #define CONFIG_SYS_FLASH_EMPTY_INFO
387 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
388                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
389
390 /* NAND Flash on IFC */
391 #define CONFIG_NAND_FSL_IFC
392 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
393 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
394 #define CONFIG_SYS_NAND_BASE            0xff800000
395 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
396
397 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
398 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
399                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
400                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
401                                 | CSPR_V)
402 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
403
404 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
405                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
406                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
407                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
408                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
409                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
410                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
411
412 #define CONFIG_SYS_NAND_ONFI_DETECTION
413
414 /* ONFI NAND Flash mode0 Timing Params */
415 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
416                                         FTIM0_NAND_TWP(0x18)   | \
417                                         FTIM0_NAND_TWCHT(0x07) | \
418                                         FTIM0_NAND_TWH(0x0a))
419 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
420                                         FTIM1_NAND_TWBE(0x39)  | \
421                                         FTIM1_NAND_TRR(0x0e)   | \
422                                         FTIM1_NAND_TRP(0x18))
423 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
424                                         FTIM2_NAND_TREH(0x0a) | \
425                                         FTIM2_NAND_TWHRE(0x1e))
426 #define CONFIG_SYS_NAND_FTIM3           0x0
427
428 #define CONFIG_SYS_NAND_DDR_LAW         11
429 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
430 #define CONFIG_SYS_MAX_NAND_DEVICE      1
431
432 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
433
434 #if defined(CONFIG_NAND)
435 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
436 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
437 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
438 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
439 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
440 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
441 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
442 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
443 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
444 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
445 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
446 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
447 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
448 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
449 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
450 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
451 #else
452 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
453 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
454 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
455 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
456 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
457 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
458 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
459 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
460 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
461 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
462 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
463 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
464 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
465 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
466 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
467 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
468 #endif
469 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
470 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
471 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
472 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
473 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
474 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
475 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
476 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
477
478 /* CPLD on IFC */
479 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
480 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
481 #define CONFIG_SYS_CSPR3_EXT    (0xf)
482 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
483                                 | CSPR_PORT_SIZE_8 \
484                                 | CSPR_MSEL_GPCM \
485                                 | CSPR_V)
486
487 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
488 #define CONFIG_SYS_CSOR3        0x0
489
490 /* CPLD Timing parameters for IFC CS3 */
491 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
492                                         FTIM0_GPCM_TEADC(0x0e) | \
493                                         FTIM0_GPCM_TEAHC(0x0e))
494 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
495                                         FTIM1_GPCM_TRAD(0x1f))
496 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
497                                         FTIM2_GPCM_TCH(0x8) | \
498                                         FTIM2_GPCM_TWP(0x1f))
499 #define CONFIG_SYS_CS3_FTIM3            0x0
500
501 #if defined(CONFIG_RAMBOOT_PBL)
502 #define CONFIG_SYS_RAMBOOT
503 #endif
504
505 /* I2C */
506 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
507 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
508 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
509 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
510
511 #define I2C_MUX_CH_DEFAULT      0x8
512 #define I2C_MUX_CH_VOL_MONITOR  0xa
513 #define I2C_MUX_CH_VSC3316_FS   0xc
514 #define I2C_MUX_CH_VSC3316_BS   0xd
515
516 /* Voltage monitor on channel 2*/
517 #define I2C_VOL_MONITOR_ADDR            0x40
518 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
519 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
520 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
521
522 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
523 #ifndef CONFIG_SPL_BUILD
524 #define CONFIG_VID
525 #endif
526 #define CONFIG_VOL_MONITOR_IR36021_SET
527 #define CONFIG_VOL_MONITOR_IR36021_READ
528 /* The lowest and highest voltage allowed for T4240RDB */
529 #define VDD_MV_MIN                      819
530 #define VDD_MV_MAX                      1212
531
532 /*
533  * eSPI - Enhanced SPI
534  */
535 #define CONFIG_SF_DEFAULT_SPEED         10000000
536 #define CONFIG_SF_DEFAULT_MODE          0
537
538 /* Qman/Bman */
539 #ifndef CONFIG_NOBQFMAN
540 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
541 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
542 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
543 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
544 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
545 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
546 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
547 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
548 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
549                                         CONFIG_SYS_BMAN_CENA_SIZE)
550 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
551 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
552 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
553 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
554 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
555 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
556 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
557 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
558 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
559 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
560 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
561                                         CONFIG_SYS_QMAN_CENA_SIZE)
562 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
563 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
564
565 #define CONFIG_SYS_DPAA_FMAN
566 #define CONFIG_SYS_DPAA_PME
567 #define CONFIG_SYS_PMAN
568 #define CONFIG_SYS_DPAA_DCE
569 #define CONFIG_SYS_DPAA_RMAN
570 #define CONFIG_SYS_INTERLAKEN
571
572 /* Default address of microcode for the Linux Fman driver */
573 #if defined(CONFIG_SPIFLASH)
574 /*
575  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
576  * env, so we got 0x110000.
577  */
578 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
579 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
580 #elif defined(CONFIG_SDCARD)
581 /*
582  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
583  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
584  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
585  */
586 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
587 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
588 #elif defined(CONFIG_NAND)
589 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
590 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
591 #else
592 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
593 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
594 #endif
595 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
596 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
597 #endif /* CONFIG_NOBQFMAN */
598
599 #ifdef CONFIG_SYS_DPAA_FMAN
600 #define CONFIG_FMAN_ENET
601 #define CONFIG_PHYLIB_10G
602 #define CONFIG_PHY_VITESSE
603 #define CONFIG_PHY_CORTINA
604 #define CONFIG_SYS_CORTINA_FW_IN_NOR
605 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
606 #define CONFIG_CORTINA_FW_LENGTH        0x40000
607 #define CONFIG_PHY_TERANETICS
608 #define SGMII_PHY_ADDR1 0x0
609 #define SGMII_PHY_ADDR2 0x1
610 #define SGMII_PHY_ADDR3 0x2
611 #define SGMII_PHY_ADDR4 0x3
612 #define SGMII_PHY_ADDR5 0x4
613 #define SGMII_PHY_ADDR6 0x5
614 #define SGMII_PHY_ADDR7 0x6
615 #define SGMII_PHY_ADDR8 0x7
616 #define FM1_10GEC1_PHY_ADDR     0x10
617 #define FM1_10GEC2_PHY_ADDR     0x11
618 #define FM2_10GEC1_PHY_ADDR     0x12
619 #define FM2_10GEC2_PHY_ADDR     0x13
620 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
621 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
622 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
623 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
624 #endif
625
626 /* SATA */
627 #ifdef CONFIG_FSL_SATA_V2
628 #define CONFIG_SYS_SATA_MAX_DEVICE      2
629 #define CONFIG_SATA1
630 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
631 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
632 #define CONFIG_SATA2
633 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
634 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
635
636 #define CONFIG_LBA48
637 #endif
638
639 #ifdef CONFIG_FMAN_ENET
640 #define CONFIG_MII              /* MII PHY management */
641 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
642 #endif
643
644 /*
645 * USB
646 */
647 #define CONFIG_USB_EHCI_FSL
648 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
649 #define CONFIG_HAS_FSL_DR_USB
650
651 #ifdef CONFIG_MMC
652 #define CONFIG_FSL_ESDHC
653 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
654 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
655 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
656 #endif
657
658
659 #define __USB_PHY_TYPE  utmi
660
661 /*
662  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
663  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
664  * interleaving. It can be cacheline, page, bank, superbank.
665  * See doc/README.fsl-ddr for details.
666  */
667 #ifdef CONFIG_ARCH_T4240
668 #define CTRL_INTLV_PREFERED 3way_4KB
669 #else
670 #define CTRL_INTLV_PREFERED cacheline
671 #endif
672
673 #define CONFIG_EXTRA_ENV_SETTINGS                               \
674         "hwconfig=fsl_ddr:"                                     \
675         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
676         "bank_intlv=auto;"                                      \
677         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
678         "netdev=eth0\0"                                         \
679         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
680         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
681         "tftpflash=tftpboot $loadaddr $uboot && "               \
682         "protect off $ubootaddr +$filesize && "                 \
683         "erase $ubootaddr +$filesize && "                       \
684         "cp.b $loadaddr $ubootaddr $filesize && "               \
685         "protect on $ubootaddr +$filesize && "                  \
686         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
687         "consoledev=ttyS0\0"                                    \
688         "ramdiskaddr=2000000\0"                                 \
689         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
690         "fdtaddr=1e00000\0"                                     \
691         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
692         "bdev=sda3\0"
693
694 #define CONFIG_HVBOOT                                   \
695         "setenv bootargs config-addr=0x60000000; "      \
696         "bootm 0x01000000 - 0x00f00000"
697
698 #define CONFIG_LINUX                                    \
699         "setenv bootargs root=/dev/ram rw "             \
700         "console=$consoledev,$baudrate $othbootargs;"   \
701         "setenv ramdiskaddr 0x02000000;"                \
702         "setenv fdtaddr 0x00c00000;"                    \
703         "setenv loadaddr 0x1000000;"                    \
704         "bootm $loadaddr $ramdiskaddr $fdtaddr"
705
706 #define CONFIG_HDBOOT                                   \
707         "setenv bootargs root=/dev/$bdev rw "           \
708         "console=$consoledev,$baudrate $othbootargs;"   \
709         "tftp $loadaddr $bootfile;"                     \
710         "tftp $fdtaddr $fdtfile;"                       \
711         "bootm $loadaddr - $fdtaddr"
712
713 #define CONFIG_NFSBOOTCOMMAND                   \
714         "setenv bootargs root=/dev/nfs rw "     \
715         "nfsroot=$serverip:$rootpath "          \
716         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
717         "console=$consoledev,$baudrate $othbootargs;"   \
718         "tftp $loadaddr $bootfile;"             \
719         "tftp $fdtaddr $fdtfile;"               \
720         "bootm $loadaddr - $fdtaddr"
721
722 #define CONFIG_RAMBOOTCOMMAND                           \
723         "setenv bootargs root=/dev/ram rw "             \
724         "console=$consoledev,$baudrate $othbootargs;"   \
725         "tftp $ramdiskaddr $ramdiskfile;"               \
726         "tftp $loadaddr $bootfile;"                     \
727         "tftp $fdtaddr $fdtfile;"                       \
728         "bootm $loadaddr $ramdiskaddr $fdtaddr"
729
730 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
731
732 #include <asm/fsl_secure_boot.h>
733
734 #endif  /* __CONFIG_H */