3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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5 * modified for TOP5200 by Reinhard Meyer, www.emk-elektronik.de
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6 * TOP5200 differences from IceCube:
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7 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
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8 * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
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9 * 1 SDRAM/DDRAM Bank up to 256 MB
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10 * local VPD I2C Bus is software driven and uses
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11 * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
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12 * FLASH is located at 0x80000000
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13 * Internal regs are at 0xfff00000
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14 * Reset jumps to 0x00000100
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 * High Level Configuration Options
43 #define CONFIG_MPC5XXX 1 /* This is an MPC5xxx CPU */
44 #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
45 #define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
47 #define CFG_MPC5XXX_CLKIN 33333333 /* ... running at 33MHz */
49 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
50 #define BOOTFLAG_WARM 0x02 /* Software reboot */
52 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
53 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
54 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
58 * Serial console configuration
60 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
61 #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
62 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
65 #ifdef CONFIG_EVAL5200 /* PCI is supported with Evaluation board only */
68 * 0x40000000 - 0x4fffffff - PCI Memory
69 * 0x50000000 - 0x50ffffff - PCI IO Space
72 # define CONFIG_PCI_PNP 1
73 # define CONFIG_PCI_SCAN_SHOW 1
75 # define CONFIG_PCI_MEM_BUS 0x40000000
76 # define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
77 # define CONFIG_PCI_MEM_SIZE 0x10000000
79 # define CONFIG_PCI_IO_BUS 0x50000000
80 # define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
81 # define CONFIG_PCI_IO_SIZE 0x01000000
83 # define ADD_PCI_CMD CFG_CMD_PCI
85 #else /* no Evaluation board */
87 # define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
94 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
95 CFG_CMD_I2C | CFG_CMD_EEPROM)
97 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
98 #include <cmd_confdefs.h>
103 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
104 #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
105 #define CONFIG_BOOTARGS "root=/dev/ram rw"
108 * IPB Bus clocking configuration.
110 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
116 * EEPROM configuration
118 #define CFG_EEPROM_PAGE_WRITE_BITS 3
119 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
121 #define CFG_I2C_EEPROM_ADDR_LEN 2
122 #define CFG_EEPROM_SIZE 0x2000
124 #define CONFIG_ENV_OVERWRITE
125 #define CONFIG_MISC_INIT_R
127 #undef CONFIG_HARD_I2C /* I2C with hardware support */
128 #define CONFIG_SOFT_I2C 1
130 #if defined (CONFIG_SOFT_I2C)
133 # define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00))
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134 # define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08))
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135 # define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c))
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136 # define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20))
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137 # define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04))
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138 # define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
139 # define I2C_READ ((DVI0&SDA0)?1:0)
140 # define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
141 # define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
142 # define I2C_DELAY {udelay(5);}
143 # define I2C_ACTIVE {DDR0|=SDA0;}
144 # define I2C_TRISTATE {DDR0&=~SDA0;}
145 # define CFG_I2C_SPEED 100000
146 # define CFG_I2C_SLAVE 0x7F
149 #if defined (CONFIG_HARD_I2C)
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150 # define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
151 # define CFG_I2C_SPEED 100000 /* 100 kHz */
152 # define CFG_I2C_SLAVE 0x7F
156 * Flash configuration, expect one 16 Megabyte Bank at most
158 #define CFG_FLASH_BASE 0xff000000
159 #define CFG_FLASH_SIZE 0x01000000
160 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
161 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0)
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163 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
165 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
166 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
168 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
171 * DRAM configuration - will be read from VPD later... TODO!
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174 /* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
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175 #define CFG_DRAM_DDR 0
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176 #define CFG_DRAM_EMODE 0
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177 #define CFG_DRAM_MODE 0x008D
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178 #define CFG_DRAM_CONTROL 0x514F0000
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179 #define CFG_DRAM_CONFIG1 0xC2233A00
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180 #define CFG_DRAM_CONFIG2 0x88B70004
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181 #define CFG_DRAM_TAP_DEL 0x08
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182 #define CFG_DRAM_RAM_SIZE 0x19
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185 /* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
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186 #define CFG_DRAM_DDR 0
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187 #define CFG_DRAM_EMODE 0
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188 #define CFG_DRAM_MODE 0x00CD
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189 #define CFG_DRAM_CONTROL 0x514F0000
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190 #define CFG_DRAM_CONFIG1 0xD2333A00
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191 #define CFG_DRAM_CONFIG2 0x8AD70004
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192 #define CFG_DRAM_TAP_DEL 0x08
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193 #define CFG_DRAM_RAM_SIZE 0x19
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197 * Environment settings
199 #define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
200 #define CFG_ENV_OFFSET 0x1000
201 #define CFG_ENV_SIZE 0x0700
202 #define CFG_I2C_EEPROM_ADDR 0x57
207 #define CFG_FACT_OFFSET 0x1800
208 #define CFG_FACT_SIZE 0x0800
209 #define CFG_I2C_FACT_ADDR 0x57
214 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
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216 #define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
217 #define CFG_SDRAM_BASE 0x00000000
218 #define CFG_DEFAULT_MBAR 0x80000000
220 /* Use SRAM until RAM will be available */
221 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
222 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
225 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
226 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
227 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
229 #define CFG_MONITOR_BASE TEXT_BASE
230 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
231 # define CFG_RAMBOOT 1
234 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
235 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
236 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
239 * Ethernet configuration
241 #define CONFIG_MPC5XXX_FEC 1
242 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
243 #define CONFIG_PHY_ADDR 0x1f
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244 #define CONFIG_PHY_TYPE 0x79c874
246 * GPIO configuration:
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247 * PSC1,2,3 predefined as UART
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249 * Ethernet 100 with MD
251 #define CFG_GPS_PORT_CONFIG 0x00058444
254 * Miscellaneous configurable options
256 #define CFG_LONGHELP /* undef to save memory */
257 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
258 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
259 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
261 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
263 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
264 #define CFG_MAXARGS 16 /* max number of command args */
265 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
267 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
268 #define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
270 #define CFG_LOAD_ADDR 0x100000 /* default load address */
272 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
275 * Various low-level settings
277 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
278 #define CFG_HID0_FINAL HID0_ICE
280 #define CFG_BOOTCS_START CFG_FLASH_BASE
281 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
282 #define CFG_BOOTCS_CFG 0x00047801
283 #define CFG_CS0_START CFG_FLASH_BASE
284 #define CFG_CS0_SIZE CFG_FLASH_SIZE
286 #define CFG_CS_BURST 0x00000000
287 #define CFG_CS_DEADCYCLE 0x33333333
289 #define CFG_RESET_ADDRESS 0x7f000000
291 #endif /* __CONFIG_H */