2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004-2005
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * High Level Configuration Options
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37 #define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38 #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
39 #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
40 #define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
42 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
44 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
45 #define BOOTFLAG_WARM 0x02 /* Software reboot */
47 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
48 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
49 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
53 * Serial console configuration
55 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
56 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
57 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
60 #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
61 #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
62 #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
63 #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
64 #define CONFIG_BOARD_EARLY_INIT_R
65 #endif /* CONFIG_STK52XX */
69 * 0x40000000 - 0x4fffffff - PCI Memory
70 * 0x50000000 - 0x50ffffff - PCI IO Space
74 #define CONFIG_PCI_PNP 1
75 /* #define CONFIG_PCI_SCAN_SHOW 1 */
77 #define CONFIG_PCI_MEM_BUS 0x40000000
78 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
79 #define CONFIG_PCI_MEM_SIZE 0x10000000
81 #define CONFIG_PCI_IO_BUS 0x50000000
82 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
83 #define CONFIG_PCI_IO_SIZE 0x01000000
85 #define CONFIG_NET_MULTI 1
86 #define CONFIG_EEPRO100 1
87 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
88 #define CONFIG_NS8382X 1
89 #endif /* CONFIG_STK52XX */
92 #define ADD_PCI_CMD CFG_CMD_PCI
102 #define CONFIG_VIDEO_SM501
103 #define CONFIG_VIDEO_SM501_32BPP
104 #define CONFIG_CFB_CONSOLE
105 #define CONFIG_VIDEO_LOGO
106 #define CONFIG_VGA_AS_SINGLE_DEVICE
107 #define CONFIG_CONSOLE_EXTRA_INFO
108 #define CONFIG_VIDEO_SW_CURSOR
109 #define CONFIG_SPLASH_SCREEN
110 #define CFG_CONSOLE_IS_IN_ENV
114 #define ADD_BMP_CMD CFG_CMD_BMP
116 #define ADD_BMP_CMD 0
120 #define CONFIG_MAC_PARTITION
121 #define CONFIG_DOS_PARTITION
122 #define CONFIG_ISO_PARTITION
125 #ifdef CONFIG_STK52XX
126 #define CONFIG_USB_OHCI
127 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
128 #define CONFIG_USB_STORAGE
130 #define ADD_USB_CMD 0
134 #define CONFIG_POST (CFG_POST_MEMORY | \
139 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
140 /* preserve space for the post_word at end of on-chip SRAM */
141 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
143 #define CFG_CMD_POST_DIAG 0
147 #if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
148 #define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
150 #define ADD_IDE_CMD 0
156 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
169 CFG_CMD_POST_DIAG | \
172 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
173 #include <cmd_confdefs.h>
175 #define CONFIG_TIMESTAMP /* display image timestamps */
177 #if (TEXT_BASE == 0xFC000000) /* Boot low */
178 # define CFG_LOWBOOT 1
184 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
186 #define CONFIG_PREBOOT "echo;" \
187 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
190 #undef CONFIG_BOOTARGS
192 #if defined (CONFIG_TQM5200_AA)
193 # define CONFIG_U_BOOT_SUFFIX "-AA\0"
194 #elif defined (CONFIG_TQM5200_AB)
195 # define CONFIG_U_BOOT_SUFFIX "-AB\0"
196 #elif defined (CONFIG_TQM5200_AC)
197 # define CONFIG_U_BOOT_SUFFIX "-AC\0"
199 # define CONFIG_U_BOOT_SUFFIX "\0"
202 #define CONFIG_EXTRA_ENV_SETTINGS \
204 "rootpath=/opt/eldk/ppc_6xx\0" \
205 "ramargs=setenv bootargs root=/dev/ram rw\0" \
206 "nfsargs=setenv bootargs root=/dev/nfs rw " \
207 "nfsroot=$(serverip):$(rootpath)\0" \
208 "addip=setenv bootargs $(bootargs) " \
209 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
210 ":$(hostname):$(netdev):off panic=1\0" \
211 "flash_self=run ramargs addip;" \
212 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
213 "flash_nfs=run nfsargs addip;" \
214 "bootm $(kernel_addr)\0" \
215 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
216 "bootfile=/tftpboot/tqm5200/uImage\0" \
217 "load=tftp 200000 $(u-boot)\0" \
218 "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \
219 "update=protect off FC000000 FC05FFFF;" \
220 "erase FC000000 FC05FFFF;" \
221 "cp.b 200000 FC000000 $(filesize);" \
222 "protect on FC000000 FC05FFFF\0" \
225 #define CONFIG_BOOTCOMMAND "run net_nfs"
228 * IPB Bus clocking configuration.
230 #define CFG_IPBSPEED_133 /* define for 133MHz speed */
232 #if defined(CFG_IPBSPEED_133)
234 * PCI Bus clocking configuration
236 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
237 * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
238 * been tested with a IPB Bus Clock of 66 MHz.
240 #define CFG_PCISPEED_66 /* define for 66MHz speed */
246 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
247 #ifdef CONFIG_TQM5200_REV100
248 #define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
250 #define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
254 * I2C clock frequency
256 * Please notice, that the resulting clock frequency could differ from the
257 * configured value. This is because the I2C clock is derived from system
258 * clock over a frequency divider with only a few divider values. U-boot
259 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
260 * approximation allways lies below the configured value, never above.
262 #define CFG_I2C_SPEED 100000 /* 100 kHz */
263 #define CFG_I2C_SLAVE 0x7F
266 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
267 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
268 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
269 * same configuration could be used.
271 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
272 #define CFG_I2C_EEPROM_ADDR_LEN 2
273 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
274 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
277 * HW-Monitor configuration on Mini-FAP
279 #if defined (CONFIG_MINIFAP)
280 #define CFG_I2C_HWMON_ADDR 0x2C
283 /* List of I2C addresses to be verified by POST */
284 #if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
285 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
287 #elif defined (CONFIG_TQM5200_AC)
288 #define I2C_ADDR_LIST { CFG_I2C_SLAVE }
291 #if defined (CONFIG_MINIFAP)
293 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
294 CFG_I2C_HWMON_ADDR, \
299 * Flash configuration
301 #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
303 /* use CFI flash driver if no module variant is spezified */
304 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
305 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
306 #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
307 #define CFG_FLASH_EMPTY_INFO
308 #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
309 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
310 #undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
312 #if !defined(CFG_LOWBOOT)
313 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
314 #else /* CFG_LOWBOOT */
315 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
316 #endif /* CFG_LOWBOOT */
317 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
319 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
320 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
324 * Environment settings
326 #define CFG_ENV_IS_IN_FLASH 1
327 #define CFG_ENV_SIZE 0x10000
328 #define CFG_ENV_SECT_SIZE 0x20000
329 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
330 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
335 #define CFG_MBAR 0xF0000000
336 #define CFG_SDRAM_BASE 0x00000000
337 #define CFG_DEFAULT_MBAR 0x80000000
339 /* Use ON-Chip SRAM until RAM will be available */
340 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
342 /* preserve space for the post_word at end of on-chip SRAM */
343 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
345 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
349 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
350 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
351 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
353 #define CFG_MONITOR_BASE TEXT_BASE
354 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
355 # define CFG_RAMBOOT 1
358 #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
359 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
360 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
363 * Ethernet configuration
365 #define CONFIG_MPC5xxx_FEC 1
367 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
369 /* #define CONFIG_FEC_10MBIT 1 */
370 #define CONFIG_PHY_ADDR 0x00
375 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
376 * Bit 0 (mask: 0x80000000): 1
377 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
378 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
379 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
380 * Use for REV200 STK52XX boards. Do not use with REV100 modules
381 * (because, there I2C1 is used as I2C bus)
382 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
383 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
384 * 000 -> All PSC2 pins are GIOPs
385 * 001 -> CAN1/2 on PSC2 pins
386 * Use for REV100 STK52xx boards
389 * use as UART. Pins PSC6_0 to PSC6_3 are used.
390 * Bits 9:11 (mask: 0x00700000):
391 * 101 -> PSC6 : Extended POST test is not available
392 * on MINI-FAP and TQM5200_IB:
393 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
394 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
395 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
398 #if defined (CONFIG_MINIFAP)
399 # define CFG_GPS_PORT_CONFIG 0x91000004
400 #elif defined (CONFIG_STK52XX)
401 # if defined (CONFIG_STK52XX_REV100)
402 # define CFG_GPS_PORT_CONFIG 0x81500014
403 # else /* STK52xx REV200 and above */
404 # if defined (CONFIG_TQM5200_REV100)
405 # error TQM5200 REV100 not supported on STK52XX REV200 or above
406 # else/* TQM5200 REV200 and above */
407 # define CFG_GPS_PORT_CONFIG 0x91500004
410 #else /* TMQ5200 Inbetriebnahme-Board */
411 # define CFG_GPS_PORT_CONFIG 0x81000004
417 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
420 * Miscellaneous configurable options
422 #define CFG_LONGHELP /* undef to save memory */
423 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
424 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
425 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
427 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
429 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
430 #define CFG_MAXARGS 16 /* max number of command args */
431 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
433 /* Enable an alternate, more extensive memory test */
434 #define CFG_ALT_MEMTEST
436 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
437 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
439 #define CFG_LOAD_ADDR 0x100000 /* default load address */
441 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
444 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
445 * which is normally part of the default commands (CFV_CMD_DFL)
450 * Various low-level settings
452 #if defined(CONFIG_MPC5200)
453 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
454 #define CFG_HID0_FINAL HID0_ICE
456 #define CFG_HID0_INIT 0
457 #define CFG_HID0_FINAL 0
460 #define CFG_BOOTCS_START CFG_FLASH_BASE
461 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
462 #ifdef CFG_PCISPEED_66
463 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
465 #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
467 #define CFG_CS0_START CFG_FLASH_BASE
468 #define CFG_CS0_SIZE CFG_FLASH_SIZE
470 /* automatic configuration of chip selects */
471 #ifdef CONFIG_CS_AUTOCONF
472 #define CONFIG_LAST_STAGE_INIT
476 * SRAM - Do not map below 2 GB in address space, because this area is used
477 * for SDRAM autosizing.
479 #if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
480 #define CFG_CS2_START 0xE5000000
481 #ifdef CONFIG_TQM5200_AB
482 #define CFG_CS2_SIZE 0x80000 /* 512 kByte */
483 #else /* CONFIG_CS_AUTOCONF */
484 #define CFG_CS2_SIZE 0x100000 /* 1 MByte */
486 #define CFG_CS2_CFG 0x0004D930
490 * Grafic controller - Do not map below 2 GB in address space, because this
491 * area is used for SDRAM autosizing.
493 #if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
494 defined (CONFIG_CS_AUTOCONF)
495 #define SM501_FB_BASE 0xE0000000
496 #define CFG_CS1_START (SM501_FB_BASE)
497 #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
498 #define CFG_CS1_CFG 0x8F48FF70
499 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
502 #define CFG_CS_BURST 0x00000000
503 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
505 #define CFG_RESET_ADDRESS 0xff000000
507 /*-----------------------------------------------------------------------
509 *-----------------------------------------------------------------------
511 #define CONFIG_USB_CLOCK 0x0001BBBB
512 #define CONFIG_USB_CONFIG 0x00001000
514 /*-----------------------------------------------------------------------
515 * IDE/ATA stuff Supports IDE harddisk
516 *-----------------------------------------------------------------------
519 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
521 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
522 #undef CONFIG_IDE_LED /* LED for ide not supported */
524 #define CONFIG_IDE_RESET /* reset for ide supported */
525 #define CONFIG_IDE_PREINIT
527 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
528 #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
530 #define CFG_ATA_IDE0_OFFSET 0x0000
532 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
534 /* Offset for data I/O */
535 #define CFG_ATA_DATA_OFFSET (0x0060)
537 /* Offset for normal register accesses */
538 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
540 /* Offset for alternate registers */
541 #define CFG_ATA_ALT_OFFSET (0x005C)
543 /* Interval between registers */
544 #define CFG_ATA_STRIDE 4
546 #endif /* __CONFIG_H */