2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004-2005
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * High Level Configuration Options
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37 #define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38 #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
39 #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
41 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
43 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
44 #define BOOTFLAG_WARM 0x02 /* Software reboot */
46 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
47 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
48 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
52 * Serial console configuration
54 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
55 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
56 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
59 #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
60 #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
61 #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
62 #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
63 #define CONFIG_BOARD_EARLY_INIT_R
64 #endif /* CONFIG_STK52XX */
68 * 0x40000000 - 0x4fffffff - PCI Memory
69 * 0x50000000 - 0x50ffffff - PCI IO Space
73 #define CONFIG_PCI_PNP 1
74 /* #define CONFIG_PCI_SCAN_SHOW 1 */
76 #define CONFIG_PCI_MEM_BUS 0x40000000
77 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
78 #define CONFIG_PCI_MEM_SIZE 0x10000000
80 #define CONFIG_PCI_IO_BUS 0x50000000
81 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
82 #define CONFIG_PCI_IO_SIZE 0x01000000
84 #define CONFIG_NET_MULTI 1
85 #define CONFIG_EEPRO100 1
86 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
87 #define CONFIG_NS8382X 1
90 #define ADD_PCI_CMD CFG_CMD_PCI
100 #define CONFIG_VIDEO_SM501
101 #define CONFIG_VIDEO_SM501_32BPP
102 #define CONFIG_CFB_CONSOLE
103 #define CONFIG_VIDEO_LOGO
104 #define CONFIG_VGA_AS_SINGLE_DEVICE
105 #define CONFIG_CONSOLE_EXTRA_INFO
106 #define CONFIG_VIDEO_SW_CURSOR
107 #define CONFIG_SPLASH_SCREEN
111 #define ADD_BMP_CMD CFG_CMD_BMP
113 #define ADD_BMP_CMD 0
117 #define CONFIG_MAC_PARTITION
118 #define CONFIG_DOS_PARTITION
119 #define CONFIG_ISO_PARTITION
122 #ifdef CONFIG_STK52XX
123 #define CONFIG_USB_OHCI
124 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
125 #define CONFIG_USB_STORAGE
127 #define ADD_USB_CMD 0
131 #define CONFIG_POST (CFG_POST_MEMORY | \
136 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
137 /* preserve space for the post_word at end of on-chip SRAM */
138 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
140 #define CFG_CMD_POST_DIAG 0
144 #if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
145 #define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
147 #define ADD_IDE_CMD 0
153 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
166 CFG_CMD_POST_DIAG | \
169 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
170 #include <cmd_confdefs.h>
172 #define CONFIG_TIMESTAMP /* display image timestamps */
174 #if (TEXT_BASE == 0xFC000000) /* Boot low */
175 # define CFG_LOWBOOT 1
181 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
183 #define CONFIG_PREBOOT "echo;" \
184 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
187 #undef CONFIG_BOOTARGS
189 #if defined (CONFIG_TQM5200_AA)
190 # define CONFIG_U_BOOT_SUFFIX "-AA\0"
191 #elif defined (CONFIG_TQM5200_AB)
192 # define CONFIG_U_BOOT_SUFFIX "-AB\0"
193 #elif defined (CONFIG_TQM5200_AC)
194 # define CONFIG_U_BOOT_SUFFIX "-AC\0"
196 # define CONFIG_U_BOOT_SUFFIX "\0"
199 #define CONFIG_EXTRA_ENV_SETTINGS \
201 "rootpath=/opt/eldk/ppc_6xx\0" \
202 "ramargs=setenv bootargs root=/dev/ram rw\0" \
203 "nfsargs=setenv bootargs root=/dev/nfs rw " \
204 "nfsroot=$(serverip):$(rootpath)\0" \
205 "addip=setenv bootargs $(bootargs) " \
206 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
207 ":$(hostname):$(netdev):off panic=1\0" \
208 "flash_self=run ramargs addip;" \
209 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
210 "flash_nfs=run nfsargs addip;" \
211 "bootm $(kernel_addr)\0" \
212 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
213 "bootfile=/tftpboot/tqm5200/uImage\0" \
214 "load=tftp 200000 $(u-boot)\0" \
215 "u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \
216 "update=protect off FC000000 FC05FFFF;" \
217 "erase FC000000 FC05FFFF;" \
218 "cp.b 200000 FC000000 $(filesize);" \
219 "protect on FC000000 FC05FFFF\0" \
222 #define CONFIG_BOOTCOMMAND "run net_nfs"
225 * IPB Bus clocking configuration.
227 #define CFG_IPBSPEED_133 /* define for 133MHz speed */
229 #if defined(CFG_IPBSPEED_133)
231 * PCI Bus clocking configuration
233 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
234 * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
235 * been tested with a IPB Bus Clock of 66 MHz.
237 #define CFG_PCISPEED_66 /* define for 66MHz speed */
243 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
244 #ifdef CONFIG_TQM5200_REV100
245 #define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
247 #define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
251 * I2C clock frequency
253 * Please notice, that the resulting clock frequency could differ from the
254 * configured value. This is because the I2C clock is derived from system
255 * clock over a frequency divider with only a few divider values. U-boot
256 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
257 * approximation allways lies below the configured value, never above.
259 #define CFG_I2C_SPEED 100000 /* 100 kHz */
260 #define CFG_I2C_SLAVE 0x7F
263 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
264 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
265 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
266 * same configuration could be used.
268 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
269 #define CFG_I2C_EEPROM_ADDR_LEN 2
270 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
271 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
274 * HW-Monitor configuration on Mini-FAP
276 #if defined (CONFIG_MINIFAP)
277 #define CFG_I2C_HWMON_ADDR 0x2C
280 /* List of I2C addresses to be verified by POST */
281 #if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
282 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
284 #elif defined (CONFIG_TQM5200_AC)
285 #define I2C_ADDR_LIST { CFG_I2C_SLAVE }
288 #if defined (CONFIG_MINIFAP)
290 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
291 CFG_I2C_HWMON_ADDR, \
296 * Flash configuration
298 #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
300 /* use CFI flash driver if no module variant is spezified */
301 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
302 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
303 #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
304 #define CFG_FLASH_EMPTY_INFO
305 #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
306 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
307 #undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
309 #if !defined(CFG_LOWBOOT)
310 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
311 #else /* CFG_LOWBOOT */
312 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
313 #endif /* CFG_LOWBOOT */
314 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
316 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
317 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
321 * Environment settings
323 #define CFG_ENV_IS_IN_FLASH 1
324 #define CFG_ENV_SIZE 0x10000
325 #define CFG_ENV_SECT_SIZE 0x20000
326 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
327 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
332 #define CFG_MBAR 0xF0000000
333 #define CFG_SDRAM_BASE 0x00000000
334 #define CFG_DEFAULT_MBAR 0x80000000
336 /* Use ON-Chip SRAM until RAM will be available */
337 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
339 /* preserve space for the post_word at end of on-chip SRAM */
340 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
342 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
346 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
347 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
348 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
350 #define CFG_MONITOR_BASE TEXT_BASE
351 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
352 # define CFG_RAMBOOT 1
355 #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
356 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
357 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
360 * Ethernet configuration
362 #define CONFIG_MPC5xxx_FEC 1
364 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
366 /* #define CONFIG_FEC_10MBIT 1 */
367 #define CONFIG_PHY_ADDR 0x00
372 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
373 * Bit 0 (mask: 0x80000000): 1
374 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
375 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
376 * Set for rev 100 modules with an onboard EEPROM (because,
377 * there I2C1 is used as I2C bus)
378 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
379 * Set for rev 200 modules
380 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
383 * use as UART. Pins PSC6_0 to PSC6_3 are used.
384 * Bits 9:11 (mask: 0x00700000):
385 * 101 -> PSC6 : Extended POST test is not available
386 * on MINI-FAP and TQM5200_IB:
387 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
388 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
389 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
392 #if defined (CONFIG_MINIFAP)
393 # define CFG_GPS_PORT_CONFIG 0x91000004
394 #elif defined (CONFIG_STK52XX)
395 # if defined (CONFIG_TQM5200_REV100)
396 # define CFG_GPS_PORT_CONFIG 0x81500004
398 # define CFG_GPS_PORT_CONFIG 0x91500004
400 #else /* TMQ5200_IP */
401 # define CFG_GPS_PORT_CONFIG 0x81000004
407 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
410 * Miscellaneous configurable options
412 #define CFG_LONGHELP /* undef to save memory */
413 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
414 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
415 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
417 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
419 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
420 #define CFG_MAXARGS 16 /* max number of command args */
421 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
423 /* Enable an alternate, more extensive memory test */
424 #define CFG_ALT_MEMTEST
426 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
427 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
429 #define CFG_LOAD_ADDR 0x100000 /* default load address */
431 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
434 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
435 * which is normally part of the default commands (CFV_CMD_DFL)
440 * Various low-level settings
442 #if defined(CONFIG_MPC5200)
443 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
444 #define CFG_HID0_FINAL HID0_ICE
446 #define CFG_HID0_INIT 0
447 #define CFG_HID0_FINAL 0
450 #define CFG_BOOTCS_START CFG_FLASH_BASE
451 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
452 #ifdef CFG_PCISPEED_66
453 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
455 #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
457 #define CFG_CS0_START CFG_FLASH_BASE
458 #define CFG_CS0_SIZE CFG_FLASH_SIZE
460 /* automatic configuration of chip selects */
461 #ifdef CONFIG_CS_AUTOCONF
462 #define CONFIG_LAST_STAGE_INIT
466 * SRAM - Do not map below 2 GB in address space, because this area is used
467 * for SDRAM autosizing.
469 #if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
470 #define CFG_CS2_START 0xE5000000
471 #ifdef CONFIG_TQM5200_AB
472 #define CFG_CS2_SIZE 0x80000 /* 512 kByte */
473 #else /* CONFIG_CS_AUTOCONF */
474 #define CFG_CS2_SIZE 0x100000 /* 1 MByte */
476 #define CFG_CS2_CFG 0x0004D930
480 * Grafic controller - Do not map below 2 GB in address space, because this
481 * area is used for SDRAM autosizing.
483 #if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
484 defined (CONFIG_CS_AUTOCONF)
485 #define SM501_FB_BASE 0xE0000000
486 #define CFG_CS1_START (SM501_FB_BASE)
487 #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
488 #define CFG_CS1_CFG 0x8F48FF70
489 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
492 #define CFG_CS_BURST 0x00000000
493 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
495 #define CFG_RESET_ADDRESS 0xff000000
497 /*-----------------------------------------------------------------------
499 *-----------------------------------------------------------------------
501 #define CONFIG_USB_CLOCK 0x0001BBBB
502 #define CONFIG_USB_CONFIG 0x00001000
504 /*-----------------------------------------------------------------------
505 * IDE/ATA stuff Supports IDE harddisk
506 *-----------------------------------------------------------------------
509 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
511 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
512 #undef CONFIG_IDE_LED /* LED for ide not supported */
514 #define CONFIG_IDE_RESET /* reset for ide supported */
515 #define CONFIG_IDE_PREINIT
517 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
518 #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
520 #define CFG_ATA_IDE0_OFFSET 0x0000
522 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
524 /* Offset for data I/O */
525 #define CFG_ATA_DATA_OFFSET (0x0060)
527 /* Offset for normal register accesses */
528 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
530 /* Offset for alternate registers */
531 #define CFG_ATA_ALT_OFFSET (0x005C)
533 /* Interval between registers */
534 #define CFG_ATA_STRIDE 4
536 #endif /* __CONFIG_H */