3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * TQM8349 board configuration file
32 * High Level Configuration Options
34 #define CONFIG_E300 1 /* E300 Family */
35 #define CONFIG_MPC83xx 1 /* MPC83xx family */
36 #define CONFIG_MPC834x 1 /* MPC834x specific */
37 #define CONFIG_MPC8349 1 /* MPC8349 specific */
38 #define CONFIG_TQM834X 1 /* TQM834X board specific */
40 #define CONFIG_SYS_TEXT_BASE 0x80000000
42 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
43 #define CONFIG_SYS_IMMR 0xff400000
45 /* System clock. Primary input clock when in PCI host mode */
46 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
50 * LCRR: DLL bypass, Clock divider is 8
52 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
54 * External Local Bus rate is
55 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
57 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
58 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
60 /* board pre init: do not call, nothing to do */
61 #undef CONFIG_BOARD_EARLY_INIT_F
63 /* detect the number of flash banks */
64 #define CONFIG_BOARD_EARLY_INIT_R
69 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
70 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
71 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
72 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
73 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
74 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
76 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
77 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
78 #define CONFIG_SYS_MEMTEST_END 0x00100000
81 * FLASH on the Local Bus
83 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
84 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
85 #undef CONFIG_SYS_FLASH_CHECKSUM
86 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
87 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
88 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
89 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
92 * FLASH bank number detection
96 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
97 * banks has to be determined at runtime and stored in a gloabl variable
98 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
99 * used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
100 * should be made sufficiently large to accomodate the number of banks that
101 * might actually be detected. Since most (all?) Flash related functions use
102 * CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
103 * defined as tqm834x_num_flash_banks.
105 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
107 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
109 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
110 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) | \
111 BR_MS_GPCM | BR_PS_32 | BR_V)
113 /* FLASH timing (0x0000_0c54) */
114 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
115 OR_GPCM_SCY_5 | OR_GPCM_TRLX)
117 #define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
119 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
121 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
123 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
125 /* disable remaining mappings */
126 #define CONFIG_SYS_BR1_PRELIM 0x00000000
127 #define CONFIG_SYS_OR1_PRELIM 0x00000000
128 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
129 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
131 #define CONFIG_SYS_BR2_PRELIM 0x00000000
132 #define CONFIG_SYS_OR2_PRELIM 0x00000000
133 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
134 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
136 #define CONFIG_SYS_BR3_PRELIM 0x00000000
137 #define CONFIG_SYS_OR3_PRELIM 0x00000000
138 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
139 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
146 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
147 # define CONFIG_SYS_RAMBOOT
149 # undef CONFIG_SYS_RAMBOOT
152 #define CONFIG_SYS_INIT_RAM_LOCK 1
153 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
154 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
156 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
157 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
159 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */
160 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
165 #define CONFIG_CONS_INDEX 1
166 #define CONFIG_SYS_NS16550
167 #define CONFIG_SYS_NS16550_SERIAL
168 #define CONFIG_SYS_NS16550_REG_SIZE 1
169 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
171 #define CONFIG_SYS_BAUDRATE_TABLE \
172 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
174 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
175 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
180 #define CONFIG_HARD_I2C /* I2C with hardware support */
181 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
182 #define CONFIG_FSL_I2C
183 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
184 #define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
185 #define CONFIG_SYS_I2C_OFFSET 0x3000
187 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
188 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
189 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
190 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
191 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
192 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
195 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
196 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
198 /* I2C SYSMON (LM75) */
199 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
200 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
201 #define CONFIG_SYS_DTT_MAX_TEMP 70
202 #define CONFIG_SYS_DTT_LOW_TEMP -30
203 #define CONFIG_SYS_DTT_HYSTERESIS 3
208 #define CONFIG_TSEC_ENET /* tsec ethernet support */
211 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
212 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
213 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
214 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
216 #if defined(CONFIG_TSEC_ENET)
218 #define CONFIG_TSEC1 1
219 #define CONFIG_TSEC1_NAME "TSEC0"
220 #define CONFIG_TSEC2 1
221 #define CONFIG_TSEC2_NAME "TSEC1"
222 #define TSEC1_PHY_ADDR 2
223 #define TSEC2_PHY_ADDR 1
224 #define TSEC1_PHYIDX 0
225 #define TSEC2_PHYIDX 0
226 #define TSEC1_FLAGS TSEC_GIGABIT
227 #define TSEC2_FLAGS TSEC_GIGABIT
229 /* Options are: TSEC[0-1] */
230 #define CONFIG_ETHPRIME "TSEC0"
232 #endif /* CONFIG_TSEC_ENET */
236 * Addresses are mapped 1-1.
240 #if defined(CONFIG_PCI)
242 #define CONFIG_PCI_PNP /* do pci plug-and-play */
243 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
245 /* PCI1 host bridge */
246 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
247 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
248 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
249 #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
250 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
251 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
252 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
253 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
254 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
256 #undef CONFIG_EEPRO100
257 #define CONFIG_EEPRO100
260 #if !defined(CONFIG_PCI_PNP)
261 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
262 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
263 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
266 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
268 #endif /* CONFIG_PCI */
273 #define CONFIG_ENV_IS_IN_FLASH 1
274 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
275 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
276 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
277 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
278 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
280 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
281 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
286 #define CONFIG_BOOTP_BOOTFILESIZE
287 #define CONFIG_BOOTP_BOOTPATH
288 #define CONFIG_BOOTP_GATEWAY
289 #define CONFIG_BOOTP_HOSTNAME
293 * Command line configuration.
295 #include <config_cmd_default.h>
297 #define CONFIG_CMD_ASKENV
298 #define CONFIG_CMD_DATE
299 #define CONFIG_CMD_DHCP
300 #define CONFIG_CMD_DTT
301 #define CONFIG_CMD_EEPROM
302 #define CONFIG_CMD_I2C
303 #define CONFIG_CMD_NFS
304 #define CONFIG_CMD_JFFS2
305 #define CONFIG_CMD_MII
306 #define CONFIG_CMD_PING
307 #define CONFIG_CMD_REGINFO
308 #define CONFIG_CMD_SNTP
310 #if defined(CONFIG_PCI)
311 #define CONFIG_CMD_PCI
314 #if defined(CONFIG_SYS_RAMBOOT)
315 #undef CONFIG_CMD_SAVEENV
316 #undef CONFIG_CMD_LOADS
320 * Miscellaneous configurable options
322 #define CONFIG_SYS_LONGHELP /* undef to save memory */
323 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
324 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
326 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
327 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
329 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
330 #ifdef CONFIG_SYS_HUSH_PARSER
331 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
334 #if defined(CONFIG_CMD_KGDB)
335 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
337 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
340 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
341 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
342 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
343 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
345 #undef CONFIG_WATCHDOG /* watchdog disabled */
347 /* pass open firmware flat tree */
348 #define CONFIG_OF_LIBFDT 1
349 #define CONFIG_OF_BOARD_SETUP 1
350 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
353 * For booting Linux, the board info and command line data
354 * have to be in the first 256 MB of memory, since this is
355 * the maximum mapped by the Linux kernel during initialization.
357 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
359 #define CONFIG_SYS_HRCW_LOW (\
360 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
361 HRCWL_DDR_TO_SCB_CLK_1X1 |\
362 HRCWL_CSB_TO_CLKIN_4X1 |\
364 HRCWL_CORE_TO_CSB_2X1)
366 #if defined(PCI_64BIT)
367 #define CONFIG_SYS_HRCW_HIGH (\
370 HRCWH_PCI1_ARBITER_ENABLE |\
371 HRCWH_PCI2_ARBITER_DISABLE |\
373 HRCWH_FROM_0X00000100 |\
374 HRCWH_BOOTSEQ_DISABLE |\
375 HRCWH_SW_WATCHDOG_DISABLE |\
376 HRCWH_ROM_LOC_LOCAL_16BIT |\
377 HRCWH_TSEC1M_IN_GMII |\
378 HRCWH_TSEC2M_IN_GMII )
380 #define CONFIG_SYS_HRCW_HIGH (\
383 HRCWH_PCI1_ARBITER_ENABLE |\
384 HRCWH_PCI2_ARBITER_DISABLE |\
386 HRCWH_FROM_0X00000100 |\
387 HRCWH_BOOTSEQ_DISABLE |\
388 HRCWH_SW_WATCHDOG_DISABLE |\
389 HRCWH_ROM_LOC_LOCAL_16BIT |\
390 HRCWH_TSEC1M_IN_GMII |\
391 HRCWH_TSEC2M_IN_GMII )
394 /* System IO Config */
395 #define CONFIG_SYS_SICRH 0
396 #define CONFIG_SYS_SICRL SICRL_LDP_A
398 /* i-cache and d-cache disabled */
399 #define CONFIG_SYS_HID0_INIT 0x000000000
400 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
401 HID0_ENABLE_INSTRUCTION_CACHE)
402 #define CONFIG_SYS_HID2 HID2_HBE
404 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
407 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
408 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
409 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
410 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
412 /* stack in DCACHE @ 512M (no backing mem) */
413 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
414 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
418 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
419 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
420 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
421 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
422 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
423 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
425 #define CONFIG_SYS_IBAT3L (0)
426 #define CONFIG_SYS_IBAT3U (0)
427 #define CONFIG_SYS_IBAT4L (0)
428 #define CONFIG_SYS_IBAT4U (0)
429 #define CONFIG_SYS_IBAT5L (0)
430 #define CONFIG_SYS_IBAT5U (0)
434 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
435 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
438 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
439 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
441 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
442 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
443 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
444 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
445 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
446 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
447 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
448 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
449 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
450 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
451 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
452 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
453 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
454 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
455 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
456 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
458 #if defined(CONFIG_CMD_KGDB)
459 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
460 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
464 * Environment Configuration
467 #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
469 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
470 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
472 #define CONFIG_BAUDRATE 115200
474 #define CONFIG_PREBOOT "echo;" \
475 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
478 #undef CONFIG_BOOTARGS
480 #define CONFIG_EXTRA_ENV_SETTINGS \
482 "hostname=tqm834x\0" \
483 "nfsargs=setenv bootargs root=/dev/nfs rw " \
484 "nfsroot=${serverip}:${rootpath}\0" \
485 "ramargs=setenv bootargs root=/dev/ram rw\0" \
486 "addip=setenv bootargs ${bootargs} " \
487 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
488 ":${hostname}:${netdev}:off panic=1\0" \
489 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
490 "flash_nfs_old=run nfsargs addip addcons;" \
491 "bootm ${kernel_addr}\0" \
492 "flash_nfs=run nfsargs addip addcons;" \
493 "bootm ${kernel_addr} - ${fdt_addr}\0" \
494 "flash_self_old=run ramargs addip addcons;" \
495 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
496 "flash_self=run ramargs addip addcons;" \
497 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
498 "net_nfs_old=tftp 400000 ${bootfile};" \
499 "run nfsargs addip addcons;bootm\0" \
500 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
501 "tftp ${fdt_addr_r} ${fdt_file}; " \
502 "run nfsargs addip addcons; " \
503 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
504 "rootpath=/opt/eldk/ppc_6xx\0" \
505 "bootfile=tqm834x/uImage\0" \
506 "fdtfile=tqm834x/tqm834x.dtb\0" \
507 "kernel_addr_r=400000\0" \
508 "fdt_addr_r=600000\0" \
509 "ramdisk_addr_r=800000\0" \
510 "kernel_addr=800C0000\0" \
511 "fdt_addr=800A0000\0" \
512 "ramdisk_addr=80300000\0" \
513 "u-boot=tqm834x/u-boot.bin\0" \
514 "load=tftp 200000 ${u-boot}\0" \
515 "update=protect off 80000000 +${filesize};" \
516 "era 80000000 +${filesize};" \
517 "cp.b 200000 80000000 ${filesize}\0" \
518 "upd=run load update\0" \
521 #define CONFIG_BOOTCOMMAND "run flash_self"
526 /* mtdparts command line support */
527 #define CONFIG_CMD_MTDPARTS
528 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
529 #define CONFIG_FLASH_CFI_MTD
530 #define MTDIDS_DEFAULT "nor0=TQM834x-0"
532 /* default mtd partition table */
533 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
534 "1m(kernel),2m(initrd),"\
537 #endif /* __CONFIG_H */