3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * TQM8349 board configuration file
16 * High Level Configuration Options
18 #define CONFIG_E300 1 /* E300 Family */
19 #define CONFIG_MPC834x 1 /* MPC834x specific */
20 #define CONFIG_MPC8349 1 /* MPC8349 specific */
22 #define CONFIG_SYS_TEXT_BASE 0x80000000
24 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
25 #define CONFIG_SYS_IMMR 0xff400000
27 /* System clock. Primary input clock when in PCI host mode */
28 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
32 * LCRR: DLL bypass, Clock divider is 8
34 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
36 * External Local Bus rate is
37 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
39 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
40 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
42 /* board pre init: do not call, nothing to do */
44 /* detect the number of flash banks */
45 #define CONFIG_BOARD_EARLY_INIT_R
50 /* DDR is system memory*/
51 #define CONFIG_SYS_DDR_BASE 0x00000000
52 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
53 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
54 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
55 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
56 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
58 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
59 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
60 #define CONFIG_SYS_MEMTEST_END 0x00100000
63 * FLASH on the Local Bus
65 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
66 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
67 #undef CONFIG_SYS_FLASH_CHECKSUM
68 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
69 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
70 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
71 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
74 * FLASH bank number detection
78 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
79 * Flash banks has to be determined at runtime and stored in a gloabl variable
80 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
81 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
82 * flash_info, and should be made sufficiently large to accomodate the number
83 * of banks that might actually be detected. Since most (all?) Flash related
84 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
85 * the board, it is defined as tqm834x_num_flash_banks.
87 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
89 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
91 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
92 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
97 /* FLASH timing (0x0000_0c54) */
98 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
103 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
105 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
106 | CONFIG_SYS_OR_TIMING_FLASH)
108 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
110 /* Window base at flash base */
111 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
113 /* disable remaining mappings */
114 #define CONFIG_SYS_BR1_PRELIM 0x00000000
115 #define CONFIG_SYS_OR1_PRELIM 0x00000000
116 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
117 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
119 #define CONFIG_SYS_BR2_PRELIM 0x00000000
120 #define CONFIG_SYS_OR2_PRELIM 0x00000000
121 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
122 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
124 #define CONFIG_SYS_BR3_PRELIM 0x00000000
125 #define CONFIG_SYS_OR3_PRELIM 0x00000000
126 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
127 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
132 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
134 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
135 # define CONFIG_SYS_RAMBOOT
137 # undef CONFIG_SYS_RAMBOOT
140 #define CONFIG_SYS_INIT_RAM_LOCK 1
141 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
142 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
144 #define CONFIG_SYS_GBL_DATA_OFFSET \
145 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
146 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
148 /* Reserve 384 kB = 3 sect. for Mon */
149 #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
150 /* Reserve 512 kB for malloc */
151 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
156 #define CONFIG_CONS_INDEX 1
157 #define CONFIG_SYS_NS16550_SERIAL
158 #define CONFIG_SYS_NS16550_REG_SIZE 1
159 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
161 #define CONFIG_SYS_BAUDRATE_TABLE \
162 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
164 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
165 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
170 #define CONFIG_SYS_I2C
171 #define CONFIG_SYS_I2C_FSL
172 #define CONFIG_SYS_FSL_I2C_SPEED 400000
173 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
174 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
176 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
177 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
178 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
179 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
183 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
184 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
189 #define CONFIG_TSEC_ENET /* tsec ethernet support */
192 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
193 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
194 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
195 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
197 #if defined(CONFIG_TSEC_ENET)
199 #define CONFIG_TSEC1 1
200 #define CONFIG_TSEC1_NAME "TSEC0"
201 #define CONFIG_TSEC2 1
202 #define CONFIG_TSEC2_NAME "TSEC1"
203 #define TSEC1_PHY_ADDR 2
204 #define TSEC2_PHY_ADDR 1
205 #define TSEC1_PHYIDX 0
206 #define TSEC2_PHYIDX 0
207 #define TSEC1_FLAGS TSEC_GIGABIT
208 #define TSEC2_FLAGS TSEC_GIGABIT
210 /* Options are: TSEC[0-1] */
211 #define CONFIG_ETHPRIME "TSEC0"
213 #endif /* CONFIG_TSEC_ENET */
215 #if defined(CONFIG_PCI)
217 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
219 /* PCI1 host bridge */
220 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
221 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
222 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
223 #define CONFIG_SYS_PCI1_MMIO_BASE \
224 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
225 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
226 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
227 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
228 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
229 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
231 #undef CONFIG_EEPRO100
232 #define CONFIG_EEPRO100
235 #if !defined(CONFIG_PCI_PNP)
236 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
237 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
238 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
241 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
243 #endif /* CONFIG_PCI */
248 #define CONFIG_ENV_ADDR \
249 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
250 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
251 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
252 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
253 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
255 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
256 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
261 #define CONFIG_BOOTP_BOOTFILESIZE
262 #define CONFIG_BOOTP_BOOTPATH
263 #define CONFIG_BOOTP_GATEWAY
264 #define CONFIG_BOOTP_HOSTNAME
267 * Miscellaneous configurable options
269 #define CONFIG_SYS_LONGHELP /* undef to save memory */
270 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
272 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
273 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
275 #undef CONFIG_WATCHDOG /* watchdog disabled */
278 * For booting Linux, the board info and command line data
279 * have to be in the first 256 MB of memory, since this is
280 * the maximum mapped by the Linux kernel during initialization.
282 /* Initial Memory map for Linux */
283 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
285 #define CONFIG_SYS_HRCW_LOW (\
286 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
287 HRCWL_DDR_TO_SCB_CLK_1X1 |\
288 HRCWL_CSB_TO_CLKIN_4X1 |\
290 HRCWL_CORE_TO_CSB_2X1)
292 #if defined(PCI_64BIT)
293 #define CONFIG_SYS_HRCW_HIGH (\
296 HRCWH_PCI1_ARBITER_ENABLE |\
297 HRCWH_PCI2_ARBITER_DISABLE |\
299 HRCWH_FROM_0X00000100 |\
300 HRCWH_BOOTSEQ_DISABLE |\
301 HRCWH_SW_WATCHDOG_DISABLE |\
302 HRCWH_ROM_LOC_LOCAL_16BIT |\
303 HRCWH_TSEC1M_IN_GMII |\
304 HRCWH_TSEC2M_IN_GMII)
306 #define CONFIG_SYS_HRCW_HIGH (\
309 HRCWH_PCI1_ARBITER_ENABLE |\
310 HRCWH_PCI2_ARBITER_DISABLE |\
312 HRCWH_FROM_0X00000100 |\
313 HRCWH_BOOTSEQ_DISABLE |\
314 HRCWH_SW_WATCHDOG_DISABLE |\
315 HRCWH_ROM_LOC_LOCAL_16BIT |\
316 HRCWH_TSEC1M_IN_GMII |\
317 HRCWH_TSEC2M_IN_GMII)
320 /* System IO Config */
321 #define CONFIG_SYS_SICRH 0
322 #define CONFIG_SYS_SICRL SICRL_LDP_A
324 /* i-cache and d-cache disabled */
325 #define CONFIG_SYS_HID0_INIT 0x000000000
326 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
327 HID0_ENABLE_INSTRUCTION_CACHE)
328 #define CONFIG_SYS_HID2 HID2_HBE
330 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
333 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
336 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
340 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
343 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
348 /* stack in DCACHE @ 512M (no backing mem) */
349 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
352 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
359 #define CONFIG_PCI_INDIRECT_BRIDGE
360 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
363 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
367 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
369 | BATL_MEMCOHERENCE \
370 | BATL_GUARDEDSTORAGE)
371 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
375 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
377 | BATL_CACHEINHIBIT \
378 | BATL_GUARDEDSTORAGE)
379 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
384 #define CONFIG_SYS_IBAT3L (0)
385 #define CONFIG_SYS_IBAT3U (0)
386 #define CONFIG_SYS_IBAT4L (0)
387 #define CONFIG_SYS_IBAT4U (0)
388 #define CONFIG_SYS_IBAT5L (0)
389 #define CONFIG_SYS_IBAT5U (0)
393 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
395 | BATL_CACHEINHIBIT \
396 | BATL_GUARDEDSTORAGE)
397 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
403 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
405 | BATL_CACHEINHIBIT \
406 | BATL_GUARDEDSTORAGE)
407 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
412 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
413 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
414 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
415 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
416 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
417 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
418 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
419 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
420 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
421 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
422 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
423 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
424 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
425 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
426 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
427 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
429 #if defined(CONFIG_CMD_KGDB)
430 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
434 * Environment Configuration
437 /* default location for tftp and bootm */
438 #define CONFIG_LOADADDR 400000
440 #define CONFIG_PREBOOT "echo;" \
441 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
444 #define CONFIG_EXTRA_ENV_SETTINGS \
446 "hostname=tqm834x\0" \
447 "nfsargs=setenv bootargs root=/dev/nfs rw " \
448 "nfsroot=${serverip}:${rootpath}\0" \
449 "ramargs=setenv bootargs root=/dev/ram rw\0" \
450 "addip=setenv bootargs ${bootargs} " \
451 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
452 ":${hostname}:${netdev}:off panic=1\0" \
453 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
454 "flash_nfs_old=run nfsargs addip addcons;" \
455 "bootm ${kernel_addr}\0" \
456 "flash_nfs=run nfsargs addip addcons;" \
457 "bootm ${kernel_addr} - ${fdt_addr}\0" \
458 "flash_self_old=run ramargs addip addcons;" \
459 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
460 "flash_self=run ramargs addip addcons;" \
461 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
462 "net_nfs_old=tftp 400000 ${bootfile};" \
463 "run nfsargs addip addcons;bootm\0" \
464 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
465 "tftp ${fdt_addr_r} ${fdt_file}; " \
466 "run nfsargs addip addcons; " \
467 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
468 "rootpath=/opt/eldk/ppc_6xx\0" \
469 "bootfile=tqm834x/uImage\0" \
470 "fdtfile=tqm834x/tqm834x.dtb\0" \
471 "kernel_addr_r=400000\0" \
472 "fdt_addr_r=600000\0" \
473 "ramdisk_addr_r=800000\0" \
474 "kernel_addr=800C0000\0" \
475 "fdt_addr=800A0000\0" \
476 "ramdisk_addr=80300000\0" \
477 "u-boot=tqm834x/u-boot.bin\0" \
478 "load=tftp 200000 ${u-boot}\0" \
479 "update=protect off 80000000 +${filesize};" \
480 "era 80000000 +${filesize};" \
481 "cp.b 200000 80000000 ${filesize}\0" \
482 "upd=run load update\0" \
485 #define CONFIG_BOOTCOMMAND "run flash_self"
490 /* mtdparts command line support */
491 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
492 #define CONFIG_FLASH_CFI_MTD
494 /* default mtd partition table */
495 #endif /* __CONFIG_H */