2 * Copyright 2005 DENX Software Engineering
3 * Wolfgang Denk <wd@denx.de>
4 * Copyright 2004 Freescale Semiconductor.
5 * (C) Copyright 2002,2003 Motorola,Inc.
6 * Xianghua Xiao <X.Xiao@motorola.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * TQM8540 board configuration file
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
37 /* High Level Configuration Options */
38 #define CONFIG_BOOKE 1 /* BOOKE */
39 #define CONFIG_E500 1 /* BOOKE e500 family */
40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41 #define CONFIG_MPC8540 1 /* MPC8540 specific */
42 #define CONFIG_TQM8540 1 /* TQM8540 board specific */
45 #define CONFIG_TSEC_ENET /* tsec ethernet support */
46 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
47 #define CONFIG_DDR_DLL /* possible DLL fix needed */
48 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
53 * Two valid values are:
57 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
58 * is likely the desired value here, so that is now the default.
59 * The board, however, can run at 66MHz. In any event, this value
60 * must match the settings of some switches. Details can be found
61 * in the README.mpc85xxads.
64 #ifndef CONFIG_SYS_CLK_FREQ
65 #define CONFIG_SYS_CLK_FREQ 33333333
69 * These can be toggled for performance analysis, otherwise use default.
71 #define CONFIG_L2_CACHE /* toggle L2 cache */
72 #define CONFIG_BTB /* toggle branch predition */
73 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
75 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
77 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
79 #undef CFG_DRAM_TEST /* memory test, takes time */
80 #define CFG_MEMTEST_START 0x00000000 /* memtest region */
81 #define CFG_MEMTEST_END 0x10000000
84 * Base addresses -- Note these are effective addresses where the
85 * actual resources get mapped (not physical addresses)
87 #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
88 #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
89 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
94 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
95 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
97 #if defined(CONFIG_SPD_EEPROM)
99 * Determine DDR configuration from I2C interface.
101 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
105 * Manually set up DDR parameters
107 #define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
108 #define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
109 #define CFG_DDR_CS0_CONFIG 0x80000102
110 #define CFG_DDR_TIMING_1 0x47445331
111 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
112 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
113 #define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
114 #define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
118 * Flash on the Local Bus
120 #define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
121 #define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
123 #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
124 #define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
126 #define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
127 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
128 #define CFG_MAX_FLASH_SECT 256 /* sectors per device */
129 #undef CFG_FLASH_CHECKSUM
130 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
131 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
133 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
135 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
141 #define CFG_FLASH_CFI_DRIVER
142 #define CFG_FLASH_CFI
143 #define CFG_FLASH_EMPTY_INFO
145 #define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
146 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
147 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
148 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
153 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
154 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
155 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
156 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
157 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
158 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
159 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
160 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
161 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
162 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
163 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
164 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
165 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
166 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
167 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
169 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
170 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
171 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
172 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
173 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
174 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
175 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
176 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
178 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
179 | CFG_LBC_LSDMR_RFCR5 \
180 | CFG_LBC_LSDMR_PRETOACT3 \
181 | CFG_LBC_LSDMR_ACTTORW3 \
182 | CFG_LBC_LSDMR_BL8 \
183 | CFG_LBC_LSDMR_WRC2 \
184 | CFG_LBC_LSDMR_CL3 \
185 | CFG_LBC_LSDMR_RFEN \
189 * SDRAM Controller configuration sequence.
191 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
192 | CFG_LBC_LSDMR_OP_PCHALL)
193 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
194 | CFG_LBC_LSDMR_OP_ARFRSH)
195 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
196 | CFG_LBC_LSDMR_OP_ARFRSH)
197 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
198 | CFG_LBC_LSDMR_OP_MRW)
199 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
200 | CFG_LBC_LSDMR_OP_NORMAL)
202 #define CONFIG_L1_INIT_RAM
203 #define CFG_INIT_RAM_LOCK 1
204 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
205 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
207 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
208 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
209 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
211 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
212 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
215 #define CONFIG_CONS_INDEX 1
216 #undef CONFIG_SERIAL_SOFTWARE_FIFO
218 #define CFG_NS16550_SERIAL
219 #define CFG_NS16550_REG_SIZE 1
220 #define CFG_NS16550_CLK get_bus_freq(0)
222 #define CFG_BAUDRATE_TABLE \
223 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
225 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
226 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
228 /* Use the HUSH parser */
229 #define CFG_HUSH_PARSER
230 #ifdef CFG_HUSH_PARSER
231 #define CFG_PROMPT_HUSH_PS2 "> "
235 #define CONFIG_HARD_I2C /* I2C with hardware support */
236 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
237 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
238 #define CFG_I2C_SLAVE 0x7F
239 #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
242 #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
243 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
247 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
249 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
250 #define CFG_I2C_EEPROM_ADDR_LEN 2
251 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
252 #define CFG_EEPROM_PAGE_WRITE_ENABLE
253 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
254 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
256 /* I2C SYSMON (LM75) */
257 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
258 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
259 #define CFG_DTT_MAX_TEMP 70
260 #define CFG_DTT_LOW_TEMP -30
261 #define CFG_DTT_HYSTERESIS 3
264 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
265 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
266 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
270 * Addresses are mapped 1-1.
272 #define CFG_PCI1_MEM_BASE 0x80000000
273 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
274 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
275 #define CFG_PCI1_IO_BASE 0xe2000000
276 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
277 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
279 #if defined(CONFIG_PCI)
281 #define CONFIG_NET_MULTI
282 #define CONFIG_PCI_PNP /* do pci plug-and-play */
284 #undef CONFIG_EEPRO100
287 #if !defined(CONFIG_PCI_PNP)
288 #define PCI_ENET0_IOADDR 0xe0000000
289 #define PCI_ENET0_MEMADDR 0xe0000000
290 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
293 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
294 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
296 #endif /* CONFIG_PCI */
299 #if defined(CONFIG_TSEC_ENET)
301 #ifndef CONFIG_NET_MULTI
302 #define CONFIG_NET_MULTI 1
305 #define CONFIG_MII 1 /* MII PHY management */
306 #define CONFIG_MPC85XX_TSEC1 1
307 #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
308 #define CONFIG_MPC85XX_TSEC2 1
309 #define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
310 #define TSEC1_PHY_ADDR 0
311 #define TSEC2_PHY_ADDR 1
312 #define TSEC1_PHYIDX 0
313 #define TSEC2_PHYIDX 0
315 #define CONFIG_MPC85XX_FEC 1
316 #define CONFIG_MPC85XX_FEC_NAME "FEC"
317 #define FEC_PHY_ADDR 3
320 #define CONFIG_HAS_ETH1
321 #define CONFIG_HAS_ETH2
323 /* Options are TSEC[0-1], FEC */
324 #define CONFIG_ETHPRIME "TSEC1"
326 #endif /* CONFIG_TSEC_ENET */
332 #define CFG_ENV_IS_IN_FLASH 1
333 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
334 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
335 #define CFG_ENV_SIZE 0x2000
336 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
337 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
339 #define CFG_NO_FLASH 1 /* Flash is not usable now */
340 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
341 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
342 #define CFG_ENV_SIZE 0x2000
345 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
346 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
348 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
350 #if defined(CFG_RAMBOOT)
351 # define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
353 # define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
359 #if defined(CONFIG_PCI)
360 # define ADD_PCI_CMD (CFG_CMD_PCI)
362 # define ADD_PCI_CMD 0
365 #define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
373 #include <cmd_confdefs.h>
375 #undef CONFIG_WATCHDOG /* watchdog disabled */
378 * Miscellaneous configurable options
380 #define CFG_LONGHELP /* undef to save memory */
381 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
382 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
384 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
385 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
387 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
390 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
391 #define CFG_MAXARGS 16 /* max number of command args */
392 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
393 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
396 * For booting Linux, the board info and command line data
397 * have to be in the first 8 MB of memory, since this is
398 * the maximum mapped by the Linux kernel during initialization.
400 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
402 /* Cache Configuration */
403 #define CFG_DCACHE_SIZE 32768
404 #define CFG_CACHELINE_SIZE 32
405 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
406 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
410 * Internal Definitions
414 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
415 #define BOOTFLAG_WARM 0x02 /* Software reboot */
417 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
418 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
419 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
423 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
425 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
427 #define CONFIG_BAUDRATE 115200
429 #define CONFIG_PREBOOT "echo;" \
430 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
433 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
435 #define CONFIG_EXTRA_ENV_SETTINGS \
438 "nfsargs=setenv bootargs root=/dev/nfs rw " \
439 "nfsroot=$serverip:$rootpath\0" \
440 "ramargs=setenv bootargs root=/dev/ram rw\0" \
441 "addip=setenv bootargs $bootargs " \
442 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
443 ":$hostname:$netdev:off panic=1\0" \
444 "addcons=setenv bootargs $bootargs " \
445 "console=$consdev,$baudrate\0" \
446 "flash_nfs=run nfsargs addip addcons;" \
447 "bootm $kernel_addr\0" \
448 "flash_self=run ramargs addip addcons;" \
449 "bootm $kernel_addr $ramdisk_addr\0" \
450 "net_nfs=tftp $loadaddr $bootfile;" \
451 "run nfsargs addip addcons;bootm\0" \
452 "rootpath=/opt/eldk/ppc_85xx\0" \
453 "bootfile=/tftpboot/tqm8540/uImage\0" \
454 "kernel_addr=FE000000\0" \
455 "ramdisk_addr=FE100000\0" \
456 "load=tftp 100000 /tftpboot/tqm8540/u-boot.bin\0" \
457 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
458 "cp.b 100000 fffc0000 40000;" \
459 "setenv filesize;saveenv\0" \
460 "upd=run load;run update\0" \
462 #define CONFIG_BOOTCOMMAND "run flash_self"
464 #endif /* __CONFIG_H */