2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37 #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE
43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
45 #define CONFIG_BOOTCOUNT_LIMIT
47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49 #define CONFIG_BOARD_TYPES 1 /* support board types */
51 #define CONFIG_PREBOOT "echo;" \
52 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
55 #undef CONFIG_BOOTARGS
57 #define CONFIG_EXTRA_ENV_SETTINGS \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
60 "nfsroot=${serverip}:${rootpath}\0" \
61 "ramargs=setenv bootargs root=/dev/ram rw\0" \
62 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \
65 "flash_nfs=run nfsargs addip;" \
66 "bootm ${kernel_addr}\0" \
67 "flash_self=run ramargs addip;" \
68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
70 "rootpath=/opt/eldk/ppc_8xx\0" \
71 "bootfile=/tftpboot/TQM855M/uImage\0" \
72 "kernel_addr=40080000\0" \
73 "ramdisk_addr=40180000\0" \
75 #define CONFIG_BOOTCOMMAND "run flash_self"
77 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
78 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
80 #undef CONFIG_WATCHDOG /* watchdog disabled */
82 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
84 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
86 /* enable I2C and select the hardware/software driver */
87 #undef CONFIG_HARD_I2C /* I2C with hardware support */
88 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
90 #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
91 #define CFG_I2C_SLAVE 0xFE
93 #ifdef CONFIG_SOFT_I2C
95 * Software (bit-bang) I2C driver configuration
97 #define PB_SCL 0x00000020 /* PB 26 */
98 #define PB_SDA 0x00000010 /* PB 27 */
100 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
101 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
102 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
103 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
104 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
105 else immr->im_cpm.cp_pbdat &= ~PB_SDA
106 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
107 else immr->im_cpm.cp_pbdat &= ~PB_SCL
108 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
109 #endif /* CONFIG_SOFT_I2C */
111 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
112 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
114 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
115 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
116 #define CFG_EEPROM_PAGE_WRITE_BITS 5
119 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
121 #define CONFIG_MAC_PARTITION
122 #define CONFIG_DOS_PARTITION
124 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
126 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
135 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
136 #include <cmd_confdefs.h>
139 * Miscellaneous configurable options
141 #define CFG_LONGHELP /* undef to save memory */
142 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
144 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
145 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
146 #ifdef CFG_HUSH_PARSER
147 #define CFG_PROMPT_HUSH_PS2 "> "
150 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
151 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
153 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
155 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
156 #define CFG_MAXARGS 16 /* max number of command args */
157 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
159 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
160 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
162 #define CFG_LOAD_ADDR 0x100000 /* default load address */
164 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
166 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
169 * Low Level Configuration Settings
170 * (address mappings, register initial values, etc.)
171 * You should know what you are doing if you make changes here.
173 /*-----------------------------------------------------------------------
174 * Internal Memory Mapped Register
176 #define CFG_IMMR 0xFFF00000
178 /*-----------------------------------------------------------------------
179 * Definitions for initial stack pointer and data area (in DPRAM)
181 #define CFG_INIT_RAM_ADDR CFG_IMMR
182 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
183 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
184 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
185 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
187 /*-----------------------------------------------------------------------
188 * Start addresses for the final memory configuration
189 * (Set up by the startup code)
190 * Please note that CFG_SDRAM_BASE _must_ start at 0
192 #define CFG_SDRAM_BASE 0x00000000
193 #define CFG_FLASH_BASE 0x40000000
194 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
195 #define CFG_MONITOR_BASE CFG_FLASH_BASE
196 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
199 * For booting Linux, the board info and command line data
200 * have to be in the first 8 MB of memory, since this is
201 * the maximum mapped by the Linux kernel during initialization.
203 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
205 /*-----------------------------------------------------------------------
208 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
209 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
211 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
212 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
214 #define CFG_ENV_IS_IN_FLASH 1
215 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
216 #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
217 #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
219 /* Address and size of Redundant Environment Sector */
220 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
221 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
223 /*-----------------------------------------------------------------------
224 * Hardware Information Block
226 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
227 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
228 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
230 /*-----------------------------------------------------------------------
231 * Cache Configuration
233 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
234 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
235 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
238 /*-----------------------------------------------------------------------
239 * SYPCR - System Protection Control 11-9
240 * SYPCR can only be written once after reset!
241 *-----------------------------------------------------------------------
242 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
244 #if defined(CONFIG_WATCHDOG)
245 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
246 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
248 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
251 /*-----------------------------------------------------------------------
252 * SIUMCR - SIU Module Configuration 11-6
253 *-----------------------------------------------------------------------
254 * PCMCIA config., multi-function pin tri-state
256 #ifndef CONFIG_CAN_DRIVER
257 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
258 #else /* we must activate GPL5 in the SIUMCR for CAN */
259 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
260 #endif /* CONFIG_CAN_DRIVER */
262 /*-----------------------------------------------------------------------
263 * TBSCR - Time Base Status and Control 11-26
264 *-----------------------------------------------------------------------
265 * Clear Reference Interrupt Status, Timebase freezing enabled
267 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
269 /*-----------------------------------------------------------------------
270 * RTCSC - Real-Time Clock Status and Control Register 11-27
271 *-----------------------------------------------------------------------
273 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
275 /*-----------------------------------------------------------------------
276 * PISCR - Periodic Interrupt Status and Control 11-31
277 *-----------------------------------------------------------------------
278 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
280 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
282 /*-----------------------------------------------------------------------
283 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
284 *-----------------------------------------------------------------------
285 * Reset PLL lock status sticky bit, timer expired status bit and timer
286 * interrupt status bit
288 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
290 /*-----------------------------------------------------------------------
291 * SCCR - System Clock and reset Control Register 15-27
292 *-----------------------------------------------------------------------
293 * Set clock output, timebase and RTC source and divider,
294 * power management and some other internal clocks
296 #define SCCR_MASK SCCR_EBDF11
297 #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
298 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
301 /*-----------------------------------------------------------------------
303 *-----------------------------------------------------------------------
306 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
307 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
308 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
309 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
310 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
311 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
312 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
313 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
315 /*-----------------------------------------------------------------------
316 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
317 *-----------------------------------------------------------------------
320 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
322 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
323 #undef CONFIG_IDE_LED /* LED for ide not supported */
324 #undef CONFIG_IDE_RESET /* reset for ide not supported */
326 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
327 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
329 #define CFG_ATA_IDE0_OFFSET 0x0000
331 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
333 /* Offset for data I/O */
334 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
336 /* Offset for normal register accesses */
337 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
339 /* Offset for alternate registers */
340 #define CFG_ATA_ALT_OFFSET 0x0100
342 /*-----------------------------------------------------------------------
344 *-----------------------------------------------------------------------
350 * Init Memory Controller:
352 * BR0/1 and OR0/1 (FLASH)
355 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
356 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
358 /* used to re-map FLASH both when starting from SRAM or FLASH:
359 * restrict access enough to keep SRAM working (if any)
360 * but not too much to meddle with FLASH accesses
362 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
363 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
368 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
369 OR_SCY_3_CLK | OR_EHTR | OR_BI)
371 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
372 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
373 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
375 #define CFG_OR1_REMAP CFG_OR0_REMAP
376 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
377 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
380 * BR2/3 and OR2/3 (SDRAM)
383 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
384 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
385 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
387 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
388 #define CFG_OR_TIMING_SDRAM 0x00000A00
390 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
391 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
393 #ifndef CONFIG_CAN_DRIVER
394 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
395 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
396 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
397 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
398 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
399 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
400 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
401 BR_PS_8 | BR_MS_UPMB | BR_V )
402 #endif /* CONFIG_CAN_DRIVER */
405 * Memory Periodic Timer Prescaler
407 * The Divider for PTA (refresh timer) configuration is based on an
408 * example SDRAM configuration (64 MBit, one bank). The adjustment to
409 * the number of chip selects (NCS) and the actually needed refresh
410 * rate is done by setting MPTPR.
412 * PTA is calculated from
413 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
415 * gclk CPU clock (not bus clock!)
416 * Trefresh Refresh cycle * 4 (four word bursts used)
418 * 4096 Rows from SDRAM example configuration
419 * 1000 factor s -> ms
420 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
421 * 4 Number of refresh cycles per period
422 * 64 Refresh cycle in ms per number of rows
423 * --------------------------------------------
424 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
426 * 50 MHz => 50.000.000 / Divider = 98
427 * 66 Mhz => 66.000.000 / Divider = 129
428 * 80 Mhz => 80.000.000 / Divider = 156
431 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
432 #define CFG_MAMR_PTA 98
435 * For 16 MBit, refresh rates could be 31.3 us
436 * (= 64 ms / 2K = 125 / quad bursts).
437 * For a simpler initialization, 15.6 us is used instead.
439 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
440 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
442 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
443 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
445 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
446 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
447 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
450 * MAMR settings for SDRAM
454 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
455 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
456 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
458 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
459 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
460 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
464 * Internal Definitions
468 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
469 #define BOOTFLAG_WARM 0x02 /* Software reboot */
471 #define CONFIG_SCC1_ENET
472 #define CONFIG_FEC_ENET
473 #define CONFIG_ETHPRIME "SCC ETHERNET"
475 #endif /* __CONFIG_H */