2 * Copyright 2005 DENX Software Engineering
3 * Wolfgang Denk <wd@denx.de>
4 * Copyright 2004 Freescale Semiconductor.
5 * (C) Copyright 2002,2003 Motorola,Inc.
6 * Xianghua Xiao <X.Xiao@motorola.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * TQM8560 board configuration file
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
37 /* High Level Configuration Options */
38 #define CONFIG_BOOKE 1 /* BOOKE */
39 #define CONFIG_E500 1 /* BOOKE e500 family */
40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41 #define CONFIG_CPM2 1 /* has CPM2 */
42 #define CONFIG_MPC8560 1 /* MPC8560 specific */
43 #define CONFIG_TQM8560 1 /* TQM8560 board specific */
46 * BIG FAT WARNING: Right now PCI seems to have a problem on the
47 * TQM8560 on the Starter Kit. So, if the board doen't come up
48 * please disable the PCI support for now. sr@denx.de, 15-09-2005
51 #define CONFIG_TSEC_ENET /* tsec ethernet support */
52 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
53 #define CONFIG_DDR_DLL /* possible DLL fix needed */
54 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
59 * Two valid values are:
63 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
64 * is likely the desired value here, so that is now the default.
65 * The board, however, can run at 66MHz. In any event, this value
66 * must match the settings of some switches. Details can be found
67 * in the README.mpc85xxads.
70 #ifndef CONFIG_SYS_CLK_FREQ
71 #define CONFIG_SYS_CLK_FREQ 33333333
75 * These can be toggled for performance analysis, otherwise use default.
77 #define CONFIG_L2_CACHE /* toggle L2 cache */
78 #define CONFIG_BTB /* toggle branch predition */
79 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
81 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
83 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
85 #undef CFG_DRAM_TEST /* memory test, takes time */
86 #define CFG_MEMTEST_START 0x00000000 /* memtest region */
87 #define CFG_MEMTEST_END 0x10000000
90 * Base addresses -- Note these are effective addresses where the
91 * actual resources get mapped (not physical addresses)
93 #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
94 #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
95 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
100 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
101 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
103 #if defined(CONFIG_SPD_EEPROM)
105 * Determine DDR configuration from I2C interface.
107 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
111 * Manually set up DDR parameters
113 #define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
114 #define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
115 #define CFG_DDR_CS0_CONFIG 0x80000102
116 #define CFG_DDR_TIMING_1 0x47445331
117 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
118 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
119 #define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
120 #define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
124 * Flash on the Local Bus
126 #define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
127 #define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
129 #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
130 #define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
132 #define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
133 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
134 #define CFG_MAX_FLASH_SECT 256 /* sectors per device */
135 #undef CFG_FLASH_CHECKSUM
136 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
137 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
139 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
141 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
147 #define CFG_FLASH_CFI_DRIVER
148 #define CFG_FLASH_CFI
149 #define CFG_FLASH_EMPTY_INFO
151 #define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
152 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
153 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
154 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
159 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
160 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
161 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
162 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
163 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
164 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
165 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
166 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
167 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
168 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
169 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
170 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
171 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
172 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
173 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
175 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
176 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
177 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
178 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
179 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
180 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
181 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
182 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
184 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
185 | CFG_LBC_LSDMR_RFCR5 \
186 | CFG_LBC_LSDMR_PRETOACT3 \
187 | CFG_LBC_LSDMR_ACTTORW3 \
188 | CFG_LBC_LSDMR_BL8 \
189 | CFG_LBC_LSDMR_WRC2 \
190 | CFG_LBC_LSDMR_CL3 \
191 | CFG_LBC_LSDMR_RFEN \
195 * SDRAM Controller configuration sequence.
197 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
198 | CFG_LBC_LSDMR_OP_PCHALL)
199 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
200 | CFG_LBC_LSDMR_OP_ARFRSH)
201 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
202 | CFG_LBC_LSDMR_OP_ARFRSH)
203 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
204 | CFG_LBC_LSDMR_OP_MRW)
205 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
206 | CFG_LBC_LSDMR_OP_NORMAL)
208 #define CONFIG_L1_INIT_RAM
209 #define CFG_INIT_RAM_LOCK 1
210 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
211 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
213 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
214 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
215 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
217 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
218 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
221 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
222 #undef CONFIG_CONS_NONE /* define if console on something else */
223 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
225 #define CONFIG_BAUDRATE 115200
227 #define CFG_BAUDRATE_TABLE \
228 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
230 /* Use the HUSH parser */
231 #define CFG_HUSH_PARSER
232 #ifdef CFG_HUSH_PARSER
233 #define CFG_PROMPT_HUSH_PS2 "> "
237 #define CONFIG_HARD_I2C /* I2C with hardware support */
238 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
239 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
240 #define CFG_I2C_SLAVE 0x7F
241 #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
244 #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
245 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
249 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
251 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
252 #define CFG_I2C_EEPROM_ADDR_LEN 2
253 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
254 #define CFG_EEPROM_PAGE_WRITE_ENABLE
255 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
256 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
258 /* I2C SYSMON (LM75) */
259 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
260 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
261 #define CFG_DTT_MAX_TEMP 70
262 #define CFG_DTT_LOW_TEMP -30
263 #define CFG_DTT_HYSTERESIS 3
266 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
267 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
268 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
272 * Addresses are mapped 1-1.
274 #define CFG_PCI1_MEM_BASE 0x80000000
275 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
276 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
277 #define CFG_PCI1_IO_BASE 0xe2000000
278 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
279 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
281 #if defined(CONFIG_PCI)
283 #define CONFIG_NET_MULTI
284 #define CONFIG_PCI_PNP /* do pci plug-and-play */
286 #define CONFIG_EEPRO100
289 #if !defined(CONFIG_PCI_PNP)
290 #define PCI_ENET0_IOADDR 0xe0000000
291 #define PCI_ENET0_MEMADDR 0xe0000000
292 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
295 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
296 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
298 #endif /* CONFIG_PCI */
301 #if defined(CONFIG_TSEC_ENET)
303 #ifndef CONFIG_NET_MULTI
304 #define CONFIG_NET_MULTI 1
307 #define CONFIG_MII 1 /* MII PHY management */
308 #define CONFIG_MPC85XX_TSEC1 1
309 #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
310 #define CONFIG_MPC85XX_TSEC2 1
311 #define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
312 #define TSEC1_PHY_ADDR 0
313 #define TSEC2_PHY_ADDR 1
314 #define TSEC1_PHYIDX 0
315 #define TSEC2_PHYIDX 0
317 #define CONFIG_MPC85XX_FEC 1
318 #define CONFIG_MPC85XX_FEC_NAME "FEC"
319 #define FEC_PHY_ADDR 3
322 #define CONFIG_HAS_ETH1
323 #define CONFIG_HAS_ETH2
325 /* Options are TSEC[0-1], FEC */
326 #define CONFIG_ETHPRIME "TSEC0"
328 #endif /* CONFIG_TSEC_ENET */
330 #define CONFIG_ETHER_ON_FCC
331 #define CONFIG_ETHER_ON_FCC3
332 #define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
333 #define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
334 #define CFG_CPMFCR_RAMTYPE 0
335 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
341 #define CFG_ENV_IS_IN_FLASH 1
342 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
343 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
344 #define CFG_ENV_SIZE 0x2000
345 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
346 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
348 #define CFG_NO_FLASH 1 /* Flash is not usable now */
349 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
350 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
351 #define CFG_ENV_SIZE 0x2000
354 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
355 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
357 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
359 #if defined(CFG_RAMBOOT)
360 # define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
362 # define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
368 #if defined(CONFIG_PCI)
369 # define ADD_PCI_CMD (CFG_CMD_PCI)
371 # define ADD_PCI_CMD 0
374 #define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
382 #include <cmd_confdefs.h>
384 #undef CONFIG_WATCHDOG /* watchdog disabled */
387 * Miscellaneous configurable options
389 #define CFG_LONGHELP /* undef to save memory */
390 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
391 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
393 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
394 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
396 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
399 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
400 #define CFG_MAXARGS 16 /* max number of command args */
401 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
402 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
405 * For booting Linux, the board info and command line data
406 * have to be in the first 8 MB of memory, since this is
407 * the maximum mapped by the Linux kernel during initialization.
409 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
411 /* Cache Configuration */
412 #define CFG_DCACHE_SIZE 32768
413 #define CFG_CACHELINE_SIZE 32
414 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
415 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
419 * Internal Definitions
423 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
424 #define BOOTFLAG_WARM 0x02 /* Software reboot */
426 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
427 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
428 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
432 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
434 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
436 #define CONFIG_BAUDRATE 115200
438 #define CONFIG_PREBOOT "echo;" \
439 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
442 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
444 #define CONFIG_EXTRA_ENV_SETTINGS \
447 "nfsargs=setenv bootargs root=/dev/nfs rw " \
448 "nfsroot=$serverip:$rootpath\0" \
449 "ramargs=setenv bootargs root=/dev/ram rw\0" \
450 "addip=setenv bootargs $bootargs " \
451 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
452 ":$hostname:$netdev:off panic=1\0" \
453 "addcons=setenv bootargs $bootargs " \
454 "console=$consdev,$baudrate\0" \
455 "flash_nfs=run nfsargs addip addcons;" \
456 "bootm $kernel_addr\0" \
457 "flash_self=run ramargs addip addcons;" \
458 "bootm $kernel_addr $ramdisk_addr\0" \
459 "net_nfs=tftp $loadaddr $bootfile;" \
460 "run nfsargs addip addcons;bootm\0" \
461 "rootpath=/opt/eldk/ppc_85xx\0" \
462 "bootfile=/tftpboot/tqm8560/uImage\0" \
463 "kernel_addr=FE000000\0" \
464 "ramdisk_addr=FE100000\0" \
465 "load=tftp 100000 /tftpboot/tqm8560/u-boot.bin\0" \
466 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
467 "cp.b 100000 fffc0000 40000;" \
468 "setenv filesize;saveenv\0" \
469 "upd=run load;run update\0" \
471 #define CONFIG_BOOTCOMMAND "run flash_self"
473 #endif /* __CONFIG_H */