3 * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 * Wolfgang Denk <wd@denx.de>
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2002,2003 Motorola,Inc.
11 * Xianghua Xiao <X.Xiao@motorola.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * TQM85xx (8560/40/55/41/48) board configuration file
39 /* High Level Configuration Options */
40 #define CONFIG_BOOKE 1 /* BOOKE */
41 #define CONFIG_E500 1 /* BOOKE e500 family */
42 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
44 #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
45 #define CONFIG_TQM8548
49 #ifndef CONFIG_TQM8548_AG
50 #define CONFIG_PCI1 /* PCI/PCI-X controller */
53 #define CONFIG_PCIE1 /* PCI Express interface */
56 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
57 #define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */
58 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
60 #define CONFIG_TSEC_ENET /* tsec ethernet support */
62 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
65 * Configuration for big NOR Flashes
67 * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
68 * Please be aware, that this changes the whole memory map (new CCSRBAR
69 * address, etc). You have to use an adapted Linux kernel or FDT blob
70 * if this option is set.
72 #undef CONFIG_TQM_BIGFLASH
75 * NAND flash support (disabled by default)
77 * Warning: NAND support will likely increase the U-Boot image size
78 * to more than 256 KB. Please adjust TEXT_BASE if necessary.
80 #ifdef CONFIG_TQM8548_BE
85 * MPC8540 and MPC8548 don't have CPM module
87 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
88 #define CONFIG_CPM2 1 /* has CPM2 */
91 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
93 #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
94 #define CONFIG_CAN_DRIVER /* CAN Driver support */
100 * Two valid values are:
104 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
105 * is likely the desired value here, so that is now the default.
106 * The board, however, can run at 66MHz. In any event, this value
107 * must match the settings of some switches. Details can be found
108 * in the README.mpc85xxads.
111 #ifndef CONFIG_SYS_CLK_FREQ
112 #define CONFIG_SYS_CLK_FREQ 33333333
116 * These can be toggled for performance analysis, otherwise use default.
118 #define CONFIG_L2_CACHE /* toggle L2 cache */
119 #define CONFIG_BTB /* toggle branch predition */
121 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
123 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
124 #define CONFIG_SYS_MEMTEST_START 0x00000000
125 #define CONFIG_SYS_MEMTEST_END 0x10000000
128 * Base addresses -- Note these are effective addresses where the
129 * actual resources get mapped (not physical addresses)
131 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
132 #ifdef CONFIG_TQM_BIGFLASH
133 #define CONFIG_SYS_CCSRBAR 0xA0000000 /* relocated CCSRBAR */
134 #else /* !CONFIG_TQM_BIGFLASH */
135 #define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
136 #endif /* CONFIG_TQM_BIGFLASH */
137 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
138 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
143 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
144 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
145 #ifdef CONFIG_TQM8548_AG
146 #define CONFIG_VERY_BIG_RAM
149 #define CONFIG_NUM_DDR_CONTROLLERS 1
150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
151 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
153 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
154 /* TQM8540 & 8560 need DLL-override */
155 #define CONFIG_DDR_DLL /* DLL fix needed */
156 #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
157 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
159 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
160 defined(CONFIG_TQM8548)
161 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
162 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
165 * Flash on the Local Bus
167 #ifdef CONFIG_TQM_BIGFLASH
168 #define CONFIG_SYS_FLASH0 0xE0000000
169 #define CONFIG_SYS_FLASH1 0xC0000000
170 #else /* !CONFIG_TQM_BIGFLASH */
171 #define CONFIG_SYS_FLASH0 0xFC000000
172 #define CONFIG_SYS_FLASH1 0xF8000000
173 #endif /* CONFIG_TQM_BIGFLASH */
174 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
176 #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
177 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
179 /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
181 * Note: According to timing specifications external addr latch delay
182 * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
184 * For other Local Bus Clocks see following table:
186 * Clock/MHz CONFIG_SYS_ORx_PRELIM
198 #ifdef CONFIG_TQM_BIGFLASH
199 #define CONFIG_SYS_BR0_PRELIM 0xE0001801 /* port size 32bit */
200 #define CONFIG_SYS_OR0_PRELIM 0xE0000040 /* 512MB Flash */
201 #define CONFIG_SYS_BR1_PRELIM 0xC0001801 /* port size 32bit */
202 #define CONFIG_SYS_OR1_PRELIM 0xE0000040 /* 512MB Flash */
203 #else /* !CONFIG_TQM_BIGFLASH */
204 #define CONFIG_SYS_BR0_PRELIM 0xfc001801 /* port size 32bit */
205 #define CONFIG_SYS_OR0_PRELIM 0xfc000040 /* 64MB Flash */
206 #define CONFIG_SYS_BR1_PRELIM 0xf8001801 /* port size 32bit */
207 #define CONFIG_SYS_OR1_PRELIM 0xfc000040 /* 64MB Flash */
208 #endif /* CONFIG_TQM_BIGFLASH */
210 #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
211 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
212 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
213 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
214 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */
216 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
217 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
218 #undef CONFIG_SYS_FLASH_CHECKSUM
219 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
220 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
222 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
225 * Note: when changing the Local Bus clock divider you have to
226 * change the timing values in CONFIG_SYS_ORx_PRELIM.
228 * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
229 * LCRR[16:17] EADC : External address delay cycles. It should be set to 2
230 * for Local Bus Clock > 83.3 MHz.
232 #define CONFIG_SYS_LBC_LCRR 0x00030008 /* LB clock ratio reg */
233 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
234 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
235 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
237 #define CONFIG_SYS_INIT_RAM_LOCK 1
238 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \
239 + 0x04010000) /* Initial RAM address */
240 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
242 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
243 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
244 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
246 #define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */
247 #define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */
250 #if defined(CONFIG_TQM8560)
252 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
253 #undef CONFIG_CONS_NONE /* define if console on something else */
254 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
256 #else /* !CONFIG_TQM8560 */
258 #define CONFIG_CONS_INDEX 1
259 #undef CONFIG_SERIAL_SOFTWARE_FIFO
260 #define CONFIG_SYS_NS16550
261 #define CONFIG_SYS_NS16550_SERIAL
262 #define CONFIG_SYS_NS16550_REG_SIZE 1
263 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
265 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
266 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
269 #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
270 #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
271 #define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
272 #define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
273 #define CONFIG_BOARD_EARLY_INIT_R 1
275 #endif /* CONFIG_TQM8560 */
277 #define CONFIG_BAUDRATE 115200
279 #define CONFIG_SYS_BAUDRATE_TABLE \
280 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
282 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
283 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
284 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
285 #ifdef CONFIG_SYS_HUSH_PARSER
286 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
289 /* pass open firmware flat tree */
290 #define CONFIG_OF_LIBFDT 1
291 #define CONFIG_OF_BOARD_SETUP 1
292 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
295 #define CONFIG_SYS_CAN_BASE (CONFIG_SYS_CCSRBAR \
296 + 0x03000000) /* CAN base address */
297 #ifdef CONFIG_CAN_DRIVER
298 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
299 #define CONFIG_SYS_OR2_CAN (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
300 #define CONFIG_SYS_BR2_CAN ((CONFIG_SYS_CAN_BASE & BR_BA) | \
301 BR_PS_8 | BR_MS_UPMC | BR_V)
302 #endif /* CONFIG_CAN_DRIVER */
307 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
308 #define CONFIG_HARD_I2C /* I2C with hardware support */
309 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
310 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
311 #define CONFIG_SYS_I2C_SLAVE 0x7F
312 #define CONFIG_SYS_I2C_NOPROBES {0x48} /* Don't probe these addrs */
313 #define CONFIG_SYS_I2C_OFFSET 0x3000
316 #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
317 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
321 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
323 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
324 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
325 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
326 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
327 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
329 /* I2C SYSMON (LM75) */
330 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
331 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
332 #define CONFIG_SYS_DTT_MAX_TEMP 70
333 #define CONFIG_SYS_DTT_LOW_TEMP -30
334 #define CONFIG_SYS_DTT_HYSTERESIS 3
338 #ifdef CONFIG_TQM_BIGFLASH
339 #define CONFIG_SYS_RIO_MEM_BASE 0xb0000000 /* base address */
340 #define CONFIG_SYS_RIO_MEM_SIZE 0x10000000 /* 256M */
341 #else /* !CONFIG_TQM_BIGFLASH */
342 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
343 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
344 #endif /* CONFIG_TQM_BIGFLASH */
345 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
346 #endif /* CONFIG_PCIE1 */
351 #define CONFIG_NAND_FSL_UPM 1
353 #define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
355 /* address distance between chip selects */
356 #define CONFIG_SYS_NAND_SELECT_DEVICE 1
357 #define CONFIG_SYS_NAND_CS_DIST 0x200
359 #define CONFIG_SYS_NAND_SIZE 0x8000
360 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_CCSRBAR + 0x03010000)
362 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
363 #define CONFIG_SYS_NAND_MAX_CHIPS 2 /* Number of chips per device */
365 /* CS3 for NAND Flash */
366 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA) | \
367 BR_PS_8 | BR_MS_UPMB | BR_V)
368 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
370 #define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
372 #endif /* CONFIG_NAND */
376 * Addresses are mapped 1-1.
378 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
379 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
380 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
381 #define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
382 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
383 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
387 * General PCI express
388 * Addresses are mapped 1-1.
390 #ifdef CONFIG_TQM_BIGFLASH
391 #define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000
392 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */
393 #define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000
394 #else /* !CONFIG_TQM_BIGFLASH */
395 #define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000
396 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
397 #define CONFIG_SYS_PCIE1_IO_BASE 0xef000000
398 #endif /* CONFIG_TQM_BIGFLASH */
399 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
400 #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE
401 #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
402 #endif /* CONFIG_PCIE1 */
404 #if defined(CONFIG_PCI)
406 #define CONFIG_PCI_PNP /* do pci plug-and-play */
408 #define CONFIG_EEPRO100
411 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
412 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
414 #endif /* CONFIG_PCI */
416 #define CONFIG_NET_MULTI 1
418 #define CONFIG_MII 1 /* MII PHY management */
419 #define CONFIG_TSEC1 1
420 #define CONFIG_TSEC1_NAME "TSEC0"
421 #define CONFIG_TSEC2 1
422 #define CONFIG_TSEC2_NAME "TSEC1"
423 #define TSEC1_PHY_ADDR 2
424 #define TSEC2_PHY_ADDR 1
425 #define TSEC1_PHYIDX 0
426 #define TSEC2_PHYIDX 0
427 #define TSEC1_FLAGS TSEC_GIGABIT
428 #define TSEC2_FLAGS TSEC_GIGABIT
429 #define FEC_PHY_ADDR 3
432 #define CONFIG_HAS_ETH0
433 #define CONFIG_HAS_ETH1
434 #define CONFIG_HAS_ETH2
436 #ifdef CONFIG_TQM8548
438 * TQM8548 has 4 ethernet ports. 4 ETSEC's.
440 * On the STK85xx Starterkit the ETSEC3/4 ports are on an
441 * additional adapter (AIO) between module and Starterkit.
443 #define CONFIG_TSEC3 1
444 #define CONFIG_TSEC3_NAME "TSEC2"
445 #define CONFIG_TSEC4 1
446 #define CONFIG_TSEC4_NAME "TSEC3"
447 #define TSEC3_PHY_ADDR 4
448 #define TSEC4_PHY_ADDR 5
449 #define TSEC3_PHYIDX 0
450 #define TSEC4_PHYIDX 0
451 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
452 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
453 #define CONFIG_HAS_ETH3
454 #define CONFIG_HAS_ETH4
455 #endif /* CONFIG_TQM8548 */
457 /* Options are TSEC[0-1], FEC */
458 #define CONFIG_ETHPRIME "TSEC0"
460 #if defined(CONFIG_TQM8540)
462 * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
463 * The FEC port is connected on the same signals as the FCC3 port
464 * of the TQM8560 to the baseboard (STK85xx Starterkit).
466 * On the STK85xx Starterkit the X47/X50 jumper has to be set to
467 * a - d (X50.2 - 3) to enable the FEC port.
469 #define CONFIG_MPC85XX_FEC 1
470 #define CONFIG_MPC85XX_FEC_NAME "FEC"
473 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
475 * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
476 * can be used at once, since only one FCC port is available on the STK85xx
479 * To use this port you have to configure U-Boot to use the FCC port 1...2
480 * and set the X47/X50 jumper to:
481 * FCC1: a - b (X47.2 - X50.2)
482 * FCC2: a - c (X50.2 - 1)
484 #define CONFIG_ETHER_ON_FCC
485 #define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
488 #if defined(CONFIG_TQM8560)
490 * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
491 * can be used at once, since only one FCC port is available on the STK85xx
494 * To use this port you have to configure U-Boot to use the FCC port 1...3
495 * and set the X47/X50 jumper to:
496 * FCC1: a - b (X47.2 - X50.2)
497 * FCC2: a - c (X50.2 - 1)
498 * FCC3: a - d (X50.2 - 3)
500 #define CONFIG_ETHER_ON_FCC
501 #define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
504 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
505 #define CONFIG_ETHER_ON_FCC1
506 #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
508 #define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
509 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
510 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
513 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
514 #define CONFIG_ETHER_ON_FCC2
515 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
517 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
518 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
519 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
522 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
523 #define CONFIG_ETHER_ON_FCC3
524 #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
526 #define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
527 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
528 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
534 #define CONFIG_ENV_IS_IN_FLASH 1
536 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
537 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
538 #define CONFIG_ENV_SIZE 0x2000
539 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
540 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
542 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
543 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
545 #define CONFIG_TIMESTAMP /* Print image info with ts */
550 #define CONFIG_BOOTP_BOOTFILESIZE
551 #define CONFIG_BOOTP_BOOTPATH
552 #define CONFIG_BOOTP_GATEWAY
553 #define CONFIG_BOOTP_HOSTNAME
557 * Use NAND-FLash as JFFS2 device
559 #define CONFIG_CMD_NAND
560 #define CONFIG_CMD_JFFS2
562 #define CONFIG_JFFS2_NAND 1
564 #ifdef CONFIG_CMD_MTDPARTS
565 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
566 #define CONFIG_FLASH_CFI_MTD
567 #define MTDIDS_DEFAULT "nand0=TQM85xx-nand"
568 #define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-"
570 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
571 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
572 #define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */
573 #endif /* CONFIG_CMD_MTDPARTS */
575 #endif /* CONFIG_NAND */
578 * Command line configuration.
580 #include <config_cmd_default.h>
582 #define CONFIG_CMD_PING
583 #define CONFIG_CMD_I2C
584 #define CONFIG_CMD_DHCP
585 #define CONFIG_CMD_NFS
586 #define CONFIG_CMD_SNTP
587 #ifndef CONFIG_TQM8548_AG
588 #define CONFIG_CMD_DATE
590 #define CONFIG_CMD_EEPROM
591 #define CONFIG_CMD_DTT
592 #define CONFIG_CMD_MII
593 #define CONFIG_CMD_REGINFO
595 #if defined(CONFIG_PCI)
596 #define CONFIG_CMD_PCI
599 #undef CONFIG_WATCHDOG /* watchdog disabled */
602 * Miscellaneous configurable options
604 #define CONFIG_SYS_LONGHELP /* undef to save memory */
605 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
606 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
608 #if defined(CONFIG_CMD_KGDB)
609 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
611 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
614 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
615 sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buf Size */
616 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
617 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
618 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
621 * For booting Linux, the board info and command line data
622 * have to be in the first 8 MB of memory, since this is
623 * the maximum mapped by the Linux kernel during initialization.
625 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
628 * Internal Definitions
632 #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
633 #define BOOTFLAG_WARM 0x02 /* Software reboot */
635 #if defined(CONFIG_CMD_KGDB)
636 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
637 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
640 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
642 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
644 #define CONFIG_PREBOOT "echo;" \
645 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
648 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
652 * Setup some board specific values for the default environment variables
655 #define CONFIG_ENV_CONSDEV "consdev=ttyCPM0\0"
657 #define CONFIG_ENV_CONSDEV "consdev=ttyS0\0"
659 #define CONFIG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
660 MK_STR(CONFIG_HOSTNAME)".dtb\0"
661 #define CONFIG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
662 #define CONFIG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
663 "uboot_addr="MK_STR(TEXT_BASE)"\0"
665 #define CONFIG_EXTRA_ENV_SETTINGS \
666 CONFIG_ENV_BOOTFILE \
667 CONFIG_ENV_FDT_FILE \
670 "nfsargs=setenv bootargs root=/dev/nfs rw " \
671 "nfsroot=$serverip:$rootpath\0" \
672 "ramargs=setenv bootargs root=/dev/ram rw\0" \
673 "addip=setenv bootargs $bootargs " \
674 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
675 ":$hostname:$netdev:off panic=1\0" \
676 "addcons=setenv bootargs $bootargs " \
677 "console=$consdev,$baudrate\0" \
678 "flash_nfs=run nfsargs addip addcons;" \
679 "bootm $kernel_addr - $fdt_addr\0" \
680 "flash_self=run ramargs addip addcons;" \
681 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
682 "net_nfs=tftp $kernel_addr_r $bootfile;" \
683 "tftp $fdt_addr_r $fdt_file;" \
684 "run nfsargs addip addcons;" \
685 "bootm $kernel_addr_r - $fdt_addr_r\0" \
686 "rootpath=/opt/eldk/ppc_85xx\0" \
687 "fdt_addr_r=900000\0" \
688 "kernel_addr_r=1000000\0" \
689 "fdt_addr=ffec0000\0" \
690 "kernel_addr=ffd00000\0" \
691 "ramdisk_addr=ff800000\0" \
693 "load=tftp 100000 $uboot\0" \
694 "update=protect off $uboot_addr +$filesize;" \
695 "erase $uboot_addr +$filesize;" \
696 "cp.b 100000 $uboot_addr $filesize" \
697 "upd=run load update\0" \
699 #define CONFIG_BOOTCOMMAND "run flash_self"
701 #endif /* __CONFIG_H */