2 * (C) Copyright 2000-2014
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_MPC866 1 /* This is a MPC866 CPU */
21 #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
23 #define CONFIG_SYS_TEXT_BASE 0x40000000
25 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
26 #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
27 #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
28 #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
29 /* (it will be used if there is no */
30 /* 'cpuclk' variable with valid value) */
32 #undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */
33 /* (function measure_gclk() */
35 #ifdef CONFIG_SYS_MEASURE_CPUCLK
36 #define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #define CONFIG_SYS_SMC_RXBUFLEN 128
41 #define CONFIG_SYS_MAXIDLE 10
43 #define CONFIG_BOOTCOUNT_LIMIT
46 #define CONFIG_BOARD_TYPES 1 /* support board types */
48 #define CONFIG_PREBOOT "echo;" \
49 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
52 #undef CONFIG_BOOTARGS
54 #define CONFIG_EXTRA_ENV_SETTINGS \
56 "nfsargs=setenv bootargs root=/dev/nfs rw " \
57 "nfsroot=${serverip}:${rootpath}\0" \
58 "ramargs=setenv bootargs root=/dev/ram rw\0" \
59 "addip=setenv bootargs ${bootargs} " \
60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
61 ":${hostname}:${netdev}:off panic=1\0" \
62 "flash_nfs=run nfsargs addip;" \
63 "bootm ${kernel_addr}\0" \
64 "flash_self=run ramargs addip;" \
65 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
66 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
67 "rootpath=/opt/eldk/ppc_8xx\0" \
68 "hostname=TQM866M\0" \
69 "bootfile=TQM866M/uImage\0" \
70 "fdt_addr=400C0000\0" \
71 "kernel_addr=40100000\0" \
72 "ramdisk_addr=40280000\0" \
73 "u-boot=TQM866M/u-image.bin\0" \
74 "load=tftp 200000 ${u-boot}\0" \
75 "update=prot off 40000000 +${filesize};" \
76 "era 40000000 +${filesize};" \
77 "cp.b 200000 40000000 ${filesize};" \
78 "sete filesize;save\0" \
80 #define CONFIG_BOOTCOMMAND "run flash_self"
82 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
83 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
85 #undef CONFIG_WATCHDOG /* watchdog disabled */
87 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
89 /* enable I2C and select the hardware/software driver */
90 #define CONFIG_SYS_I2C
91 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
92 #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
93 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
96 * Software (bit-bang) I2C driver configuration
98 #define PB_SCL 0x00000020 /* PB 26 */
99 #define PB_SDA 0x00000010 /* PB 27 */
101 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
102 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
103 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
104 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
105 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
106 else immr->im_cpm.cp_pbdat &= ~PB_SDA
107 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
108 else immr->im_cpm.cp_pbdat &= ~PB_SCL
109 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
111 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
112 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
113 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
114 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
119 #define CONFIG_BOOTP_SUBNETMASK
120 #define CONFIG_BOOTP_GATEWAY
121 #define CONFIG_BOOTP_HOSTNAME
122 #define CONFIG_BOOTP_BOOTPATH
123 #define CONFIG_BOOTP_BOOTFILESIZE
125 #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
127 #define CONFIG_TIMESTAMP /* but print image timestmps */
130 * Command line configuration.
132 #define CONFIG_CMD_EEPROM
133 #define CONFIG_CMD_IDE
134 #define CONFIG_CMD_JFFS2
136 #define CONFIG_NETCONSOLE
139 * Miscellaneous configurable options
141 #define CONFIG_SYS_LONGHELP /* undef to save memory */
143 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
145 #if defined(CONFIG_CMD_KGDB)
146 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
148 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
151 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
152 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
154 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
155 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
157 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
160 * Low Level Configuration Settings
161 * (address mappings, register initial values, etc.)
162 * You should know what you are doing if you make changes here.
164 /*-----------------------------------------------------------------------
165 * Internal Memory Mapped Register
167 #define CONFIG_SYS_IMMR 0xFFF00000
169 /*-----------------------------------------------------------------------
170 * Definitions for initial stack pointer and data area (in DPRAM)
172 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
173 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
174 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
175 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
177 /*-----------------------------------------------------------------------
178 * Start addresses for the final memory configuration
179 * (Set up by the startup code)
180 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
182 #define CONFIG_SYS_SDRAM_BASE 0x00000000
183 #define CONFIG_SYS_FLASH_BASE 0x40000000
184 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
186 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
189 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization.
193 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
195 /*-----------------------------------------------------------------------
198 /* use CFI flash driver */
199 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
200 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
201 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
202 #define CONFIG_SYS_FLASH_EMPTY_INFO
203 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
204 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
205 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
207 #define CONFIG_ENV_IS_IN_FLASH 1
208 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
209 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
210 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
212 /* Address and size of Redundant Environment Sector */
213 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
214 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
216 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
218 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
220 /*-----------------------------------------------------------------------
221 * Dynamic MTD partition support
223 #define CONFIG_CMD_MTDPARTS
224 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
225 #define CONFIG_FLASH_CFI_MTD
226 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
228 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
234 /*-----------------------------------------------------------------------
235 * Hardware Information Block
237 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
238 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
239 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
241 /*-----------------------------------------------------------------------
242 * Cache Configuration
244 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
245 #if defined(CONFIG_CMD_KGDB)
246 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
249 /*-----------------------------------------------------------------------
250 * SYPCR - System Protection Control 11-9
251 * SYPCR can only be written once after reset!
252 *-----------------------------------------------------------------------
253 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
255 #if defined(CONFIG_WATCHDOG)
256 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
257 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
259 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
262 /*-----------------------------------------------------------------------
263 * SIUMCR - SIU Module Configuration 11-6
264 *-----------------------------------------------------------------------
265 * PCMCIA config., multi-function pin tri-state
267 #ifndef CONFIG_CAN_DRIVER
268 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
269 #else /* we must activate GPL5 in the SIUMCR for CAN */
270 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
271 #endif /* CONFIG_CAN_DRIVER */
273 /*-----------------------------------------------------------------------
274 * TBSCR - Time Base Status and Control 11-26
275 *-----------------------------------------------------------------------
276 * Clear Reference Interrupt Status, Timebase freezing enabled
278 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
280 /*-----------------------------------------------------------------------
281 * PISCR - Periodic Interrupt Status and Control 11-31
282 *-----------------------------------------------------------------------
283 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
285 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
287 /*-----------------------------------------------------------------------
288 * SCCR - System Clock and reset Control Register 15-27
289 *-----------------------------------------------------------------------
290 * Set clock output, timebase and RTC source and divider,
291 * power management and some other internal clocks
293 #define SCCR_MASK SCCR_EBDF11
294 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
295 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
298 /*-----------------------------------------------------------------------
300 *-----------------------------------------------------------------------
303 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
304 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
305 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
306 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
307 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
308 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
309 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
310 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
312 /*-----------------------------------------------------------------------
313 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
314 *-----------------------------------------------------------------------
317 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
318 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
320 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
321 #undef CONFIG_IDE_LED /* LED for ide not supported */
322 #undef CONFIG_IDE_RESET /* reset for ide not supported */
324 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
325 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
327 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
329 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
331 /* Offset for data I/O */
332 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
334 /* Offset for normal register accesses */
335 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
337 /* Offset for alternate registers */
338 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
340 /*-----------------------------------------------------------------------
342 *-----------------------------------------------------------------------
345 #define CONFIG_SYS_DER 0
348 * Init Memory Controller:
350 * BR0/1 and OR0/1 (FLASH)
353 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
354 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
356 /* used to re-map FLASH both when starting from SRAM or FLASH:
357 * restrict access enough to keep SRAM working (if any)
358 * but not too much to meddle with FLASH accesses
360 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
361 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
364 * FLASH timing: Default value of OR0 after reset
366 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
367 OR_SCY_15_CLK | OR_TRLX)
369 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
370 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
371 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
373 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
374 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
375 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
378 * BR2/3 and OR2/3 (SDRAM)
381 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
382 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
383 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
385 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
386 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
388 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
389 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
391 #ifndef CONFIG_CAN_DRIVER
392 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
393 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
394 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
395 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
396 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
397 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
398 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
399 BR_PS_8 | BR_MS_UPMB | BR_V )
400 #endif /* CONFIG_CAN_DRIVER */
403 * 4096 Rows from SDRAM example configuration
404 * 1000 factor s -> ms
405 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
406 * 4 Number of refresh cycles per period
407 * 64 Refresh cycle in ms per number of rows
409 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
412 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
414 * CPUclock(MHz) * 31.2
415 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
416 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
418 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
419 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
420 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
421 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
423 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
424 * be met also in the default configuration, i.e. if environment variable
425 * 'cpuclk' is not set.
427 #define CONFIG_SYS_MAMR_PTA 97
430 * Memory Periodic Timer Prescaler Register (MPTPR) values.
432 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
433 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
434 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
435 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
438 * MAMR settings for SDRAM
442 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
443 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
444 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
446 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
447 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
448 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
449 /* 10 column SDRAM */
450 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
451 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
452 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
454 #define CONFIG_SCC1_ENET
455 #define CONFIG_FEC_ENET
456 #define CONFIG_ETHPRIME "SCC"
458 #define CONFIG_HWCONFIG 1
460 #endif /* __CONFIG_H */