2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
12 * QorIQ uCP1020-xx boards configuration file
17 #define CONFIG_SYS_GENERIC_BOARD
18 #define CONFIG_DISPLAY_BOARDINFO
20 #define CONFIG_FSL_ELBC
22 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
23 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
24 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
25 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
26 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
27 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
29 #if defined(CONFIG_TARTGET_UCP1020T1)
31 #define CONFIG_UCP1020_REV_1_3
33 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
36 #define CONFIG_TSEC_ENET
39 #define CONFIG_HAS_ETH0
40 #define CONFIG_HAS_ETH1
41 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
42 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
43 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
44 #define CONFIG_IPADDR 10.80.41.229
45 #define CONFIG_SERVERIP 10.80.41.227
46 #define CONFIG_NETMASK 255.255.252.0
47 #define CONFIG_ETHPRIME "eTSEC3"
49 #ifndef CONFIG_SPI_FLASH
50 #define CONFIG_SPI_FLASH y
52 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
55 #define CONFIG_SYS_L2_SIZE (256 << 10)
57 #define CONFIG_LAST_STAGE_INIT
59 #if !defined(CONFIG_DONGLE)
60 #define CONFIG_SILENT_CONSOLE
65 #if defined(CONFIG_TARGET_UCP1020)
67 #define CONFIG_UCP1020
68 #define CONFIG_UCP1020_REV_1_3
70 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
73 #define CONFIG_TSEC_ENET
77 #define CONFIG_HAS_ETH0
78 #define CONFIG_HAS_ETH1
79 #define CONFIG_HAS_ETH2
80 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
81 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
82 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
83 #define CONFIG_IPADDR 192.168.1.81
84 #define CONFIG_IPADDR1 192.168.1.82
85 #define CONFIG_IPADDR2 192.168.1.83
86 #define CONFIG_SERVERIP 192.168.1.80
87 #define CONFIG_GATEWAYIP 102.168.1.1
88 #define CONFIG_NETMASK 255.255.255.0
89 #define CONFIG_ETHPRIME "eTSEC1"
91 #ifndef CONFIG_SPI_FLASH
92 #define CONFIG_SPI_FLASH y
94 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
97 #define CONFIG_SYS_L2_SIZE (256 << 10)
99 #define CONFIG_LAST_STAGE_INIT
104 #define CONFIG_RAMBOOT_SDCARD
105 #define CONFIG_SYS_RAMBOOT
106 #define CONFIG_SYS_EXTRA_ENV_RELOC
107 #define CONFIG_SYS_TEXT_BASE 0x11000000
108 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
111 #ifdef CONFIG_SPIFLASH
112 #define CONFIG_RAMBOOT_SPIFLASH
113 #define CONFIG_SYS_RAMBOOT
114 #define CONFIG_SYS_EXTRA_ENV_RELOC
115 #define CONFIG_SYS_TEXT_BASE 0x11000000
116 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
119 #ifndef CONFIG_SYS_TEXT_BASE
120 #define CONFIG_SYS_TEXT_BASE 0xeff80000
122 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
124 #ifndef CONFIG_RESET_VECTOR_ADDRESS
125 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
128 #ifndef CONFIG_SYS_MONITOR_BASE
129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
132 /* High Level Configuration Options */
135 /* #define CONFIG_MPC85xx */
139 #define CONFIG_FSL_LAW
141 #define CONFIG_ENV_OVERWRITE
143 #define CONFIG_CMD_SATA
144 #define CONFIG_SATA_SIL
145 #define CONFIG_SYS_SATA_MAX_DEVICE 2
146 #define CONFIG_LIBATA
149 #define CONFIG_SYS_CLK_FREQ 66666666
150 #define CONFIG_DDR_CLK_FREQ 66666666
152 #define CONFIG_HWCONFIG
154 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
155 #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
156 #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */
158 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
159 * there will be one entry in this array for each two (dummy) sensors in
160 * CONFIG_DTT_SENSORS.
162 * For uCP1020 module:
163 * - only one ADM1021/NCT72
165 * - conversion rate 0x02 = 0.25 conversions/second
166 * - ALERT output disabled
167 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
168 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
170 #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \
171 0x02, 0, 1, 0, 85, 1, 0, 85} }
173 #define CONFIG_CMD_DTT
176 * These can be toggled for performance analysis, otherwise use default.
178 #define CONFIG_L2_CACHE
181 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
183 #define CONFIG_ENABLE_36BIT_PHYS
185 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
186 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
187 #define CONFIG_PANIC_HANG /* do not reset board on panic */
189 #define CONFIG_SYS_CCSRBAR 0xffe00000
190 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
192 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
194 #ifdef CONFIG_SPL_BUILD
195 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
199 #define CONFIG_DDR_ECC_ENABLE
200 #define CONFIG_SYS_FSL_DDR3
201 #ifndef CONFIG_DDR_ECC_ENABLE
202 #define CONFIG_SYS_DDR_RAW_TIMING
203 #define CONFIG_DDR_SPD
205 #define CONFIG_SYS_SPD_BUS_NUM 1
206 #undef CONFIG_FSL_DDR_INTERACTIVE
208 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
209 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
210 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
211 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
212 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
214 #define CONFIG_NUM_DDR_CONTROLLERS 1
215 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
217 /* Default settings for DDR3 */
218 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
219 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
220 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
221 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
222 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
223 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
225 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
226 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
227 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
228 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
230 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
231 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
232 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
233 #define CONFIG_SYS_DDR_RCW_1 0x00000000
234 #define CONFIG_SYS_DDR_RCW_2 0x00000000
235 #ifdef CONFIG_DDR_ECC_ENABLE
236 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
238 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
240 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
241 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
242 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
244 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
245 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
246 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
247 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
248 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
249 #define CONFIG_SYS_DDR_MODE_1 0x40461520
250 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
251 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
253 #undef CONFIG_CLOCKS_IN_MHZ
258 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
259 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
260 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
261 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
263 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
264 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
265 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
269 * Local Bus Definitions
271 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
272 #define CONFIG_SYS_FLASH_BASE 0xec000000
274 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
276 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
279 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
281 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
282 #define CONFIG_SYS_FLASH_QUIET_TEST
283 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
285 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
287 #undef CONFIG_SYS_FLASH_CHECKSUM
288 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
289 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
291 #define CONFIG_FLASH_CFI_DRIVER
292 #define CONFIG_SYS_FLASH_CFI
293 #define CONFIG_SYS_FLASH_EMPTY_INFO
294 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
296 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
298 #define CONFIG_SYS_INIT_RAM_LOCK
299 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
300 /* Initial L1 address */
301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
304 /* Size of used area in RAM */
305 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
307 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
308 GENERATED_GBL_DATA_SIZE)
309 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
311 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
312 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
314 #define CONFIG_SYS_PMC_BASE 0xff980000
315 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
316 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
318 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
319 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
322 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
323 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
324 #ifdef CONFIG_NAND_FSL_ELBC
325 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
326 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
329 /* Serial Port - controlled on board with jumper J8
333 #define CONFIG_CONS_INDEX 1
334 #undef CONFIG_SERIAL_SOFTWARE_FIFO
335 #define CONFIG_SYS_NS16550
336 #define CONFIG_SYS_NS16550_SERIAL
337 #define CONFIG_SYS_NS16550_REG_SIZE 1
338 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
339 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
340 #define CONFIG_NS16550_MIN_FUNCTIONS
343 #define CONFIG_SYS_BAUDRATE_TABLE \
344 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
346 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
347 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
349 /* Use the HUSH parser */
350 #define CONFIG_SYS_HUSH_PARSER
353 * Pass open firmware flat tree
355 #define CONFIG_OF_LIBFDT
356 #define CONFIG_OF_BOARD_SETUP
357 #define CONFIG_OF_STDOUT_VIA_ALIAS
359 /* new uImage format support */
361 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
364 #define CONFIG_SYS_I2C
365 #define CONFIG_SYS_I2C_FSL
366 #define CONFIG_SYS_FSL_I2C_SPEED 400000
367 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
368 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
369 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
370 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
371 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
372 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
373 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
375 #define CONFIG_RTC_DS1337
376 #define CONFIG_SYS_RTC_DS1337_NOOSC
377 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
378 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
379 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
380 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
383 * eSPI - Enhanced SPI
385 #define CONFIG_HARD_SPI
386 #define CONFIG_FSL_ESPI
388 #define CONFIG_SPI_FLASH_SST 1
389 #define CONFIG_SPI_FLASH_STMICRO 1
390 #define CONFIG_SPI_FLASH_WINBOND 1
391 #define CONFIG_CMD_SF 1
392 #define CONFIG_CMD_SPI 1
393 #define CONFIG_SF_DEFAULT_SPEED 10000000
394 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
396 #if defined(CONFIG_PCI)
399 * Memory space is mapped 1-1, but I/O space must start from 0.
402 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
403 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
404 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
405 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
406 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
407 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
408 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
409 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
410 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
411 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
413 /* controller 1, Slot 2, tgtid 1, Base address a000 */
414 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
415 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
416 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
417 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
418 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
419 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
420 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
421 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
422 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
424 #define CONFIG_PCI_PNP /* do pci plug-and-play */
425 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
426 #define CONFIG_CMD_PCI
428 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
429 #define CONFIG_DOS_PARTITION
430 #endif /* CONFIG_PCI */
435 #ifdef CONFIG_ENV_FIT_UCBOOT
437 #define CONFIG_ENV_IS_IN_FLASH
438 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
439 #define CONFIG_ENV_SIZE 0x20000
440 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
444 #define CONFIG_ENV_SPI_BUS 0
445 #define CONFIG_ENV_SPI_CS 0
446 #define CONFIG_ENV_SPI_MAX_HZ 10000000
447 #define CONFIG_ENV_SPI_MODE 0
449 #ifdef CONFIG_RAMBOOT_SPIFLASH
451 #define CONFIG_ENV_IS_IN_SPI_FLASH
452 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
453 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
454 #define CONFIG_ENV_SECT_SIZE 0x1000
456 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
457 /* Address and size of Redundant Environment Sector */
458 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
459 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
462 #elif defined(CONFIG_RAMBOOT_SDCARD)
463 #define CONFIG_ENV_IS_IN_MMC
464 #define CONFIG_FSL_FIXED_MMC_LOCATION
465 #define CONFIG_ENV_SIZE 0x2000
466 #define CONFIG_SYS_MMC_ENV_DEV 0
468 #elif defined(CONFIG_SYS_RAMBOOT)
469 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
470 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
471 #define CONFIG_ENV_SIZE 0x2000
474 #define CONFIG_ENV_IS_IN_FLASH
475 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
476 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
477 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
478 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
479 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
480 /* Address and size of Redundant Environment Sector */
481 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
482 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
487 #endif /* CONFIG_ENV_FIT_UCBOOT */
489 #define CONFIG_LOADS_ECHO /* echo on for serial download */
490 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
493 * Command line configuration.
495 #include <config_cmd_default.h>
497 #define CONFIG_CMD_IRQ
498 #define CONFIG_CMD_PING
499 #define CONFIG_CMD_I2C
500 #define CONFIG_CMD_MII
501 #define CONFIG_CMD_DATE
502 #define CONFIG_CMD_ELF
503 #define CONFIG_CMD_I2C
504 #define CONFIG_CMD_IRQ
505 #define CONFIG_CMD_MII
506 #define CONFIG_CMD_PING
507 #define CONFIG_CMD_REGINFO
508 #define CONFIG_CMD_ERRATA
509 #define CONFIG_CMD_CRAMFS
510 #define CONFIG_CRAMFS_CMDLINE
515 #define CONFIG_HAS_FSL_DR_USB
517 #if defined(CONFIG_HAS_FSL_DR_USB)
518 #define CONFIG_USB_EHCI
520 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
522 #ifdef CONFIG_USB_EHCI
523 #define CONFIG_CMD_USB
524 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
525 #define CONFIG_USB_EHCI_FSL
526 #define CONFIG_USB_STORAGE
530 #undef CONFIG_WATCHDOG /* watchdog disabled */
533 #define CONFIG_FSL_ESDHC
534 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
535 #define CONFIG_CMD_MMC
536 #define CONFIG_MMC_SPI
537 #define CONFIG_CMD_MMC_SPI
538 #define CONFIG_GENERIC_MMC
541 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
542 #define CONFIG_CMD_EXT2
543 #define CONFIG_CMD_FAT
544 #define CONFIG_DOS_PARTITION
547 /* Misc Extra Settings */
548 #define CONFIG_CMD_GPIO 1
549 #undef CONFIG_WATCHDOG /* watchdog disabled */
552 * Miscellaneous configurable options
554 #define CONFIG_SYS_LONGHELP /* undef to save memory */
555 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
556 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
557 #define CONFIG_SYS_PROMPT "B$ " /* Monitor Command Prompt */
558 #if defined(CONFIG_CMD_KGDB)
559 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
561 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
563 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
564 /* Print Buffer Size */
565 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
566 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
567 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
570 * For booting Linux, the board info and command line data
571 * have to be in the first 64 MB of memory, since this is
572 * the maximum mapped by the Linux kernel during initialization.
574 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
575 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
577 #if defined(CONFIG_CMD_KGDB)
578 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
579 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
583 * Environment Configuration
586 #if defined(CONFIG_TSEC_ENET)
588 #if defined(CONFIG_UCP1020_REV_1_2)
589 #define CONFIG_PHY_MICREL_KSZ9021
590 #elif defined(CONFIG_UCP1020_REV_1_3)
591 #define CONFIG_PHY_MICREL_KSZ9031
593 #error "UCP1020 module revision is not defined !!!"
596 #define CONFIG_CMD_DHCP
597 #define CONFIG_BOOTP_SERVERIP
599 #define CONFIG_MII /* MII PHY management */
600 #define CONFIG_TSEC1_NAME "eTSEC1"
601 #define CONFIG_TSEC2_NAME "eTSEC2"
602 #define CONFIG_TSEC3_NAME "eTSEC3"
604 #define TSEC1_PHY_ADDR 4
605 #define TSEC2_PHY_ADDR 0
606 #define TSEC2_PHY_ADDR_SGMII 0x00
607 #define TSEC3_PHY_ADDR 6
609 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
610 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
611 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
613 #define TSEC1_PHYIDX 0
614 #define TSEC2_PHYIDX 0
615 #define TSEC3_PHYIDX 0
617 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
621 #define CONFIG_HOSTNAME UCP1020
622 #define CONFIG_ROOTPATH "/opt/nfsroot"
623 #define CONFIG_BOOTFILE "uImage"
624 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
626 /* default location for tftp and bootm */
627 #define CONFIG_LOADADDR 1000000
632 #define CONFIG_AUTOBOOT_KEYED
633 #define CONFIG_AUTOBOOT_STOP_STR "\x1b"
634 #define DEBUG_BOOTKEYS 0
635 #undef CONFIG_AUTOBOOT_DELAY_STR
636 #undef CONFIG_BOOTARGS
637 #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
638 "press \"<Esc>\" to stop\n", bootdelay
640 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
642 #define CONFIG_BAUDRATE 115200
644 #if defined(CONFIG_DONGLE)
646 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
647 #define CONFIG_EXTRA_ENV_SETTINGS \
648 "bootcmd=run prog_spi_mbrbootcramfs\0" \
649 "bootfile=uImage\0" \
650 "consoledev=ttyS0\0" \
651 "cramfsfile=image.cramfs\0" \
652 "dtbaddr=0x00c00000\0" \
653 "dtbfile=image.dtb\0" \
654 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
655 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
656 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
657 "fileaddr=0x01000000\0" \
658 "filesize=0x00080000\0" \
659 "flashmbr=sf probe 0; " \
660 "tftp $loadaddr $mbr; " \
661 "sf erase $mbr_offset +$filesize; " \
662 "sf write $loadaddr $mbr_offset $filesize\0" \
663 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
664 "protect off $nor_recoveryaddr +$filesize; " \
665 "erase $nor_recoveryaddr +$filesize; " \
666 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
667 "protect on $nor_recoveryaddr +$filesize\0 " \
668 "flashuboot=tftp $ubootaddr $ubootfile; " \
669 "protect off $nor_ubootaddr +$filesize; " \
670 "erase $nor_ubootaddr +$filesize; " \
671 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
672 "protect on $nor_ubootaddr +$filesize\0 " \
673 "flashworking=tftp $workingaddr $cramfsfile; " \
674 "protect off $nor_workingaddr +$filesize; " \
675 "erase $nor_workingaddr +$filesize; " \
676 "cp.b $workingaddr $nor_workingaddr $filesize; " \
677 "protect on $nor_workingaddr +$filesize\0 " \
678 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
679 "kerneladdr=0x01100000\0" \
680 "kernelfile=uImage\0" \
681 "loadaddr=0x01000000\0" \
682 "mbr=uCP1020d.mbr\0" \
683 "mbr_offset=0x00000000\0" \
684 "mmbr=uCP1020Quiet.mbr\0" \
686 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
688 "mmc write $loadaddr 1 1\0" \
689 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
690 "mmc erase 0x40 0x400; " \
691 "mmc write $loadaddr 0x40 0x400\0" \
693 "nor_recoveryaddr=0xEC0A0000\0" \
694 "nor_ubootaddr=0xEFF80000\0" \
695 "nor_workingaddr=0xECFA0000\0" \
696 "norbootrecovery=setenv bootargs $recoverybootargs" \
697 " console=$consoledev,$baudrate $othbootargs; " \
698 "run norloadrecovery; " \
699 "bootm $kerneladdr - $dtbaddr\0" \
700 "norbootworking=setenv bootargs $workingbootargs" \
701 " console=$consoledev,$baudrate $othbootargs; " \
702 "run norloadworking; " \
703 "bootm $kerneladdr - $dtbaddr\0" \
704 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
705 "setenv cramfsaddr $nor_recoveryaddr; " \
706 "cramfsload $dtbaddr $dtbfile; " \
707 "cramfsload $kerneladdr $kernelfile\0" \
708 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
709 "setenv cramfsaddr $nor_workingaddr; " \
710 "cramfsload $dtbaddr $dtbfile; " \
711 "cramfsload $kerneladdr $kernelfile\0" \
712 "prog_spi_mbr=run spi__mbr\0" \
713 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
714 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
715 "run spi__cramfs\0" \
716 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
717 " console=$consoledev,$baudrate $othbootargs; " \
718 "tftp $rootfsaddr $rootfsfile; " \
719 "tftp $loadaddr $kernelfile; " \
720 "tftp $dtbaddr $dtbfile; " \
721 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
722 "ramdisk_size=120000\0" \
723 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
724 "recoveryaddr=0x02F00000\0" \
725 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
726 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
727 "mw.l 0xffe0f008 0x00400000\0" \
728 "rootfsaddr=0x02F00000\0" \
729 "rootfsfile=rootfs.ext2.gz.uboot\0" \
730 "rootpath=/opt/nfsroot\0" \
731 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
732 "protect off 0xeC000000 +$filesize; " \
733 "erase 0xEC000000 +$filesize; " \
734 "cp.b $loadaddr 0xEC000000 $filesize; " \
735 "cmp.b $loadaddr 0xEC000000 $filesize; " \
736 "protect on 0xeC000000 +$filesize\0" \
737 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
738 "protect off 0xeFF80000 +$filesize; " \
739 "erase 0xEFF80000 +$filesize; " \
740 "cp.b $loadaddr 0xEFF80000 $filesize; " \
741 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
742 "protect on 0xeFF80000 +$filesize\0" \
743 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
744 "sf probe 0; sf erase 0x8000 +$filesize; " \
745 "sf write $loadaddr 0x8000 $filesize\0" \
746 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
747 "protect off 0xec0a0000 +$filesize; " \
748 "erase 0xeC0A0000 +$filesize; " \
749 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
750 "protect on 0xec0a0000 +$filesize\0" \
751 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
752 "sf probe 1; sf erase 0 +$filesize; " \
753 "sf write $loadaddr 0 $filesize\0" \
754 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
755 "sf probe 0; sf erase 0 +$filesize; " \
756 "sf write $loadaddr 0 $filesize\0" \
757 "tftpflash=tftpboot $loadaddr $uboot; " \
758 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
759 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
760 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
761 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
762 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
763 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
764 "ubootaddr=0x01000000\0" \
765 "ubootfile=u-boot.bin\0" \
766 "ubootd=u-boot4dongle.bin\0" \
767 "upgrade=run flashworking\0" \
768 "usb_phy_type=ulpi\0 " \
769 "workingaddr=0x02F00000\0" \
770 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
774 #if defined(CONFIG_UCP1020T1)
776 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
777 #define CONFIG_EXTRA_ENV_SETTINGS \
778 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
779 "bootfile=uImage\0" \
780 "consoledev=ttyS0\0" \
781 "cramfsfile=image.cramfs\0" \
782 "dtbaddr=0x00c00000\0" \
783 "dtbfile=image.dtb\0" \
784 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
785 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
786 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
787 "fileaddr=0x01000000\0" \
788 "filesize=0x00080000\0" \
789 "flashmbr=sf probe 0; " \
790 "tftp $loadaddr $mbr; " \
791 "sf erase $mbr_offset +$filesize; " \
792 "sf write $loadaddr $mbr_offset $filesize\0" \
793 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
794 "protect off $nor_recoveryaddr +$filesize; " \
795 "erase $nor_recoveryaddr +$filesize; " \
796 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
797 "protect on $nor_recoveryaddr +$filesize\0 " \
798 "flashuboot=tftp $ubootaddr $ubootfile; " \
799 "protect off $nor_ubootaddr +$filesize; " \
800 "erase $nor_ubootaddr +$filesize; " \
801 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
802 "protect on $nor_ubootaddr +$filesize\0 " \
803 "flashworking=tftp $workingaddr $cramfsfile; " \
804 "protect off $nor_workingaddr +$filesize; " \
805 "erase $nor_workingaddr +$filesize; " \
806 "cp.b $workingaddr $nor_workingaddr $filesize; " \
807 "protect on $nor_workingaddr +$filesize\0 " \
808 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
809 "kerneladdr=0x01100000\0" \
810 "kernelfile=uImage\0" \
811 "loadaddr=0x01000000\0" \
812 "mbr=uCP1020.mbr\0" \
813 "mbr_offset=0x00000000\0" \
815 "nor_recoveryaddr=0xEC0A0000\0" \
816 "nor_ubootaddr=0xEFF80000\0" \
817 "nor_workingaddr=0xECFA0000\0" \
818 "norbootrecovery=setenv bootargs $recoverybootargs" \
819 " console=$consoledev,$baudrate $othbootargs; " \
820 "run norloadrecovery; " \
821 "bootm $kerneladdr - $dtbaddr\0" \
822 "norbootworking=setenv bootargs $workingbootargs" \
823 " console=$consoledev,$baudrate $othbootargs; " \
824 "run norloadworking; " \
825 "bootm $kerneladdr - $dtbaddr\0" \
826 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
827 "setenv cramfsaddr $nor_recoveryaddr; " \
828 "cramfsload $dtbaddr $dtbfile; " \
829 "cramfsload $kerneladdr $kernelfile\0" \
830 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
831 "setenv cramfsaddr $nor_workingaddr; " \
832 "cramfsload $dtbaddr $dtbfile; " \
833 "cramfsload $kerneladdr $kernelfile\0" \
834 "othbootargs=quiet\0" \
835 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
836 " console=$consoledev,$baudrate $othbootargs; " \
837 "tftp $rootfsaddr $rootfsfile; " \
838 "tftp $loadaddr $kernelfile; " \
839 "tftp $dtbaddr $dtbfile; " \
840 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
841 "ramdisk_size=120000\0" \
842 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
843 "recoveryaddr=0x02F00000\0" \
844 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
845 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
846 "mw.l 0xffe0f008 0x00400000\0" \
847 "rootfsaddr=0x02F00000\0" \
848 "rootfsfile=rootfs.ext2.gz.uboot\0" \
849 "rootpath=/opt/nfsroot\0" \
851 "tftpflash=tftpboot $loadaddr $uboot; " \
852 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
853 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
854 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
855 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
856 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
857 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
858 "ubootaddr=0x01000000\0" \
859 "ubootfile=u-boot.bin\0" \
860 "upgrade=run flashworking\0" \
861 "workingaddr=0x02F00000\0" \
862 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
864 #else /* For Arcturus Modules */
866 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
867 #define CONFIG_EXTRA_ENV_SETTINGS \
868 "bootcmd=run norkernel\0" \
869 "bootfile=uImage\0" \
870 "consoledev=ttyS0\0" \
871 "dtbaddr=0x00c00000\0" \
872 "dtbfile=image.dtb\0" \
873 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
874 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
875 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
876 "fileaddr=0x01000000\0" \
877 "filesize=0x00080000\0" \
878 "flashmbr=sf probe 0; " \
879 "tftp $loadaddr $mbr; " \
880 "sf erase $mbr_offset +$filesize; " \
881 "sf write $loadaddr $mbr_offset $filesize\0" \
882 "flashuboot=tftp $loadaddr $ubootfile; " \
883 "protect off $nor_ubootaddr0 +$filesize; " \
884 "erase $nor_ubootaddr0 +$filesize; " \
885 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
886 "protect on $nor_ubootaddr0 +$filesize; " \
887 "protect off $nor_ubootaddr1 +$filesize; " \
888 "erase $nor_ubootaddr1 +$filesize; " \
889 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
890 "protect on $nor_ubootaddr1 +$filesize\0 " \
891 "format0=protect off $part0base +$part0size; " \
892 "erase $part0base +$part0size\0" \
893 "format1=protect off $part1base +$part1size; " \
894 "erase $part1base +$part1size\0" \
895 "format2=protect off $part2base +$part2size; " \
896 "erase $part2base +$part2size\0" \
897 "format3=protect off $part3base +$part3size; " \
898 "erase $part3base +$part3size\0" \
899 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
900 "kerneladdr=0x01100000\0" \
901 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
902 "kernelfile=uImage\0" \
903 "loadaddr=0x01000000\0" \
904 "mbr=uCP1020.mbr\0" \
905 "mbr_offset=0x00000000\0" \
907 "nor_ubootaddr0=0xEC000000\0" \
908 "nor_ubootaddr1=0xEFF80000\0" \
909 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
910 "run norkernelload; " \
911 "bootm $kerneladdr - $dtbaddr\0" \
912 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
913 "setenv cramfsaddr $part0base; " \
914 "cramfsload $dtbaddr $dtbfile; " \
915 "cramfsload $kerneladdr $kernelfile\0" \
916 "part0base=0xEC100000\0" \
917 "part0size=0x00700000\0" \
918 "part1base=0xEC800000\0" \
919 "part1size=0x02000000\0" \
920 "part2base=0xEE800000\0" \
921 "part2size=0x00800000\0" \
922 "part3base=0xEF000000\0" \
923 "part3size=0x00F80000\0" \
924 "partENVbase=0xEC080000\0" \
925 "partENVsize=0x00080000\0" \
926 "program0=tftp part0-000000.bin; " \
927 "protect off $part0base +$filesize; " \
928 "erase $part0base +$filesize; " \
929 "cp.b $loadaddr $part0base $filesize; " \
930 "echo Verifying...; " \
931 "cmp.b $loadaddr $part0base $filesize\0" \
932 "program1=tftp part1-000000.bin; " \
933 "protect off $part1base +$filesize; " \
934 "erase $part1base +$filesize; " \
935 "cp.b $loadaddr $part1base $filesize; " \
936 "echo Verifying...; " \
937 "cmp.b $loadaddr $part1base $filesize\0" \
938 "program2=tftp part2-000000.bin; " \
939 "protect off $part2base +$filesize; " \
940 "erase $part2base +$filesize; " \
941 "cp.b $loadaddr $part2base $filesize; " \
942 "echo Verifying...; " \
943 "cmp.b $loadaddr $part2base $filesize\0" \
944 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
945 " console=$consoledev,$baudrate $othbootargs; " \
946 "tftp $rootfsaddr $rootfsfile; " \
947 "tftp $loadaddr $kernelfile; " \
948 "tftp $dtbaddr $dtbfile; " \
949 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
950 "ramdisk_size=120000\0" \
951 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
952 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
953 "mw.l 0xffe0f008 0x00400000\0" \
954 "rootfsaddr=0x02F00000\0" \
955 "rootfsfile=rootfs.ext2.gz.uboot\0" \
956 "rootpath=/opt/nfsroot\0" \
957 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
958 "sf probe 0; sf erase 0 +$filesize; " \
959 "sf write $loadaddr 0 $filesize\0" \
960 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
961 "protect off 0xeC000000 +$filesize; " \
962 "erase 0xEC000000 +$filesize; " \
963 "cp.b $loadaddr 0xEC000000 $filesize; " \
964 "cmp.b $loadaddr 0xEC000000 $filesize; " \
965 "protect on 0xeC000000 +$filesize\0" \
966 "tftpflash=tftpboot $loadaddr $uboot; " \
967 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
968 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
969 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
970 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
971 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
972 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
973 "ubootfile=u-boot.bin\0" \
974 "upgrade=run flashuboot\0" \
975 "usb_phy_type=ulpi\0 " \
977 "setenv bootargs root=/dev/nfs rw " \
978 "nfsroot=$serverip:$rootpath " \
979 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
980 "console=$consoledev,$baudrate $othbootargs;" \
981 "tftp $loadaddr $bootfile;" \
982 "tftp $fdtaddr $fdtfile;" \
983 "bootm $loadaddr - $fdtaddr\0" \
985 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
986 "console=$consoledev,$baudrate $othbootargs;" \
988 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
989 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
990 "bootm $loadaddr - $fdtaddr\0" \
992 "setenv bootargs root=/dev/ram rw " \
993 "console=$consoledev,$baudrate $othbootargs " \
994 "ramdisk_size=$ramdisk_size;" \
996 "fatload usb 0:2 $loadaddr $bootfile;" \
997 "fatload usb 0:2 $fdtaddr $fdtfile;" \
998 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
999 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
1000 "boot_usb_ext2 = " \
1001 "setenv bootargs root=/dev/ram rw " \
1002 "console=$consoledev,$baudrate $othbootargs " \
1003 "ramdisk_size=$ramdisk_size;" \
1005 "ext2load usb 0:4 $loadaddr $bootfile;" \
1006 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1007 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1008 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
1010 "setenv bootargs root=/dev/$jffs2nor rw " \
1011 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
1012 "bootm $norbootaddr - $norfdtaddr\0 " \
1014 "setenv bootargs root=/dev/ram rw " \
1015 "console=$consoledev,$baudrate $othbootargs " \
1016 "ramdisk_size=$ramdisk_size;" \
1017 "tftp $ramdiskaddr $ramdiskfile;" \
1018 "tftp $loadaddr $bootfile;" \
1019 "tftp $fdtaddr $fdtfile;" \
1020 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
1025 #endif /* __CONFIG_H */