2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
8 * SPDX-License-Identifier: GPL-2.0+
15 * High Level Configuration Options
19 #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
20 #define CONFIG_A4M072 1 /* ... on A4M072 board */
21 #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
23 #define CONFIG_SYS_TEXT_BASE 0xFE000000
25 #define CONFIG_MISC_INIT_R
27 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
29 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
32 * Serial console configuration
34 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
35 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
36 /* define to enable silent console */
37 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
41 * 0x40000000 - 0x4fffffff - PCI Memory
42 * 0x50000000 - 0x50ffffff - PCI IO Space
45 #if defined(CONFIG_PCI)
46 #define CONFIG_PCI_SCAN_SHOW 1
47 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
49 #define CONFIG_PCI_MEM_BUS 0x40000000
50 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
51 #define CONFIG_PCI_MEM_SIZE 0x10000000
53 #define CONFIG_PCI_IO_BUS 0x50000000
54 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
55 #define CONFIG_PCI_IO_SIZE 0x01000000
58 #define CONFIG_SYS_XLB_PIPELINING 1
60 #undef CONFIG_EEPRO100
63 #define CONFIG_USB_OHCI_NEW
64 #define CONFIG_SYS_OHCI_BE_CONTROLLER
65 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
66 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
67 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
68 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
69 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
71 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
76 #define CONFIG_BOOTP_BOOTFILESIZE
77 #define CONFIG_BOOTP_BOOTPATH
78 #define CONFIG_BOOTP_GATEWAY
79 #define CONFIG_BOOTP_HOSTNAME
82 * Command line configuration.
84 #define CONFIG_CMD_IDE
86 #if defined(CONFIG_PCI)
87 #define CONFIG_CMD_PCI
90 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
91 #define CONFIG_SYS_LOWBOOT 1
92 #define CONFIG_SYS_LOWBOOT32 1
99 #define CONFIG_SYS_AUTOLOAD "n"
101 #undef CONFIG_BOOTARGS
102 #define CONFIG_PREBOOT "run try_update"
104 #define CONFIG_EXTRA_ENV_SETTINGS \
105 "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
106 "cf1=diskboot 200000 0:1\0" \
107 "bootcmd_cf1=run bcf1\0" \
108 "bcf=setenv bootargs root=/dev/hda3\0" \
109 "bootcmd_nfs=run bnfs\0" \
110 "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
112 "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;" \
113 "run norargs addip; run bk\0" \
114 "bnfs=nfs 200000 ${rootpath}/boot/uImage;" \
115 "run nfsargs addip ; run bk\0" \
116 "nfsargs=setenv bootargs root=/dev/nfs rw " \
117 "nfsroot=${serverip}:${rootpath}\0" \
118 "try_update=usb start;sleep 2;usb start;sleep 1;" \
119 "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;" \
121 "env_addr=FE060000\0" \
122 "kernel_addr=FE100000\0" \
123 "rootfs_addr=FE200000\0" \
124 "add_mtd=setenv bootargs ${bootargs} mtdparts=" \
125 "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
126 "bcf1=run cf1; run bcf; run addip; run bk\0" \
127 "add_consolespec=setenv bootargs ${bootargs} " \
128 "console=/dev/null quiet\0" \
129 "addip=if test -n ${ethaddr};" \
130 "then if test -n ${ipaddr};" \
131 "then setenv bootargs ${bootargs} " \
132 "ip=${ipaddr}:${serverip}:${gatewayip}:"\
133 "${netmask}:${hostname}:${netdev}:off;" \
136 "setenv bootargs ${bootargs} no_ethaddr;" \
140 "bootcmd=run bootcmd_nor\0" \
143 * IPB Bus clocking configuration.
145 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
148 * Flash configuration
150 #define CONFIG_SYS_FLASH_BASE 0xFE000000
151 #define CONFIG_SYS_FLASH_SIZE 0x02000000
152 #if !defined(CONFIG_SYS_LOWBOOT)
153 #error "CONFIG_SYS_LOWBOOT not defined?"
154 #else /* CONFIG_SYS_LOWBOOT */
155 #if defined(CONFIG_SYS_LOWBOOT32)
156 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
158 #endif /* CONFIG_SYS_LOWBOOT */
160 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
161 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
162 #define CONFIG_FLASH_CFI_DRIVER
163 #define CONFIG_SYS_FLASH_CFI
164 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
165 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START}
166 #define CONFIG_SYS_FLASH_BANKS_SIZES {CONFIG_SYS_CS0_SIZE}
169 * Environment settings
171 #define CONFIG_ENV_IS_IN_FLASH 1
172 #define CONFIG_ENV_SIZE 0x10000
173 #define CONFIG_ENV_SECT_SIZE 0x20000
174 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
175 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
177 #define CONFIG_ENV_OVERWRITE 1
182 #define CONFIG_SYS_MBAR 0xF0000000
183 #define CONFIG_SYS_SDRAM_BASE 0x00000000
184 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
186 /* Use SRAM until RAM will be available */
187 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
188 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
190 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
194 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
195 # define CONFIG_SYS_RAMBOOT 1
198 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
199 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
200 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
203 * Ethernet configuration
205 #define CONFIG_MPC5xxx_FEC 1
206 #define CONFIG_MPC5xxx_FEC_MII100
208 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
210 /* #define CONFIG_MPC5xxx_FEC_MII10 */
211 #define CONFIG_PHY_ADDR 0x1f
212 #define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */
217 #define CONFIG_SYS_GPS_PORT_CONFIG 0x18000004
220 * Miscellaneous configurable options
222 #define CONFIG_CMDLINE_EDITING 1
223 #define CONFIG_SYS_LONGHELP /* undef to save memory */
224 #if defined(CONFIG_CMD_KGDB)
225 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
227 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
229 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
230 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
231 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
233 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
234 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
236 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
238 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
239 #if defined(CONFIG_CMD_KGDB)
240 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
244 * Various low-level settings
246 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
247 #define CONFIG_SYS_HID0_FINAL HID0_ICE
248 /* Flash at CSBoot, CS0 */
249 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
250 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
251 #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
252 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
253 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
254 /* External SRAM at CS1 */
255 #define CONFIG_SYS_CS1_START 0x62000000
256 #define CONFIG_SYS_CS1_SIZE 0x00400000
257 #define CONFIG_SYS_CS1_CFG 0x00009930
258 #define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START
259 #define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
260 /* LED display at CS7 */
261 #define CONFIG_SYS_CS7_START 0x6a000000
262 #define CONFIG_SYS_CS7_SIZE (64*1024)
263 #define CONFIG_SYS_CS7_CFG 0x0000bf30
265 #define CONFIG_SYS_CS_BURST 0x00000000
266 #define CONFIG_SYS_CS_DEADCYCLE 0x33333003
268 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
270 /*-----------------------------------------------------------------------
272 *-----------------------------------------------------------------------
274 #define CONFIG_USB_CLOCK 0x0001BBBB
275 #define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */
277 /*-----------------------------------------------------------------------
278 * IDE/ATA stuff Supports IDE harddisk
279 *-----------------------------------------------------------------------
282 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
284 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
285 #undef CONFIG_IDE_LED /* LED for ide not supported */
287 #define CONFIG_IDE_PREINIT
289 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
290 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
292 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
294 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
296 /* Offset for data I/O */
297 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
299 /* Offset for normal register accesses */
300 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
302 /* Offset for alternate registers */
303 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
305 /* Interval between registers */
306 #define CONFIG_SYS_ATA_STRIDE 4
308 #define CONFIG_ATAPI 1
310 /*-----------------------------------------------------------------------
311 * Open firmware flat tree support
312 *-----------------------------------------------------------------------
314 #define OF_CPU "PowerPC,5200@0"
315 #define OF_SOC "soc5200@f0000000"
316 #define OF_TBCLK (bd->bi_busfreq / 4)
317 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
319 /* Support for the 7-segment display */
320 #define CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_CS7_START
321 #define CONFIG_SHOW_ACTIVITY /* used for display realization */
323 #define CONFIG_SHOW_BOOT_PROGRESS
325 #endif /* __CONFIG_H */