2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * High Level Configuration Options
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
37 #define CONFIG_A4M072 1 /* ... on A4M072 board */
38 #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
40 #define CONFIG_MISC_INIT_R
42 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
44 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
47 * Serial console configuration
49 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
50 #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
51 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
52 /* define to enable silent console */
53 #define CONFIG_SILENT_CONSOLE
54 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
58 * 0x40000000 - 0x4fffffff - PCI Memory
59 * 0x50000000 - 0x50ffffff - PCI IO Space
63 #if defined(CONFIG_PCI)
64 #define CONFIG_PCI_PNP 1
65 #define CONFIG_PCI_SCAN_SHOW 1
66 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
68 #define CONFIG_PCI_MEM_BUS 0x40000000
69 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
70 #define CONFIG_PCI_MEM_SIZE 0x10000000
72 #define CONFIG_PCI_IO_BUS 0x50000000
73 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
74 #define CONFIG_PCI_IO_SIZE 0x01000000
77 #define CONFIG_SYS_XLB_PIPELINING 1
79 #undef CONFIG_NET_MULTI
80 #undef CONFIG_EEPRO100
83 #define CONFIG_MAC_PARTITION
84 #define CONFIG_DOS_PARTITION
87 #define CONFIG_USB_OHCI_NEW
88 #define CONFIG_USB_STORAGE
89 #define CONFIG_SYS_OHCI_BE_CONTROLLER
90 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
91 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
92 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
93 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
94 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
96 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
101 #define CONFIG_BOOTP_BOOTFILESIZE
102 #define CONFIG_BOOTP_BOOTPATH
103 #define CONFIG_BOOTP_GATEWAY
104 #define CONFIG_BOOTP_HOSTNAME
108 * Command line configuration.
110 #include <config_cmd_default.h>
112 #define CONFIG_CMD_EEPROM
113 #define CONFIG_CMD_FAT
114 #define CONFIG_CMD_I2C
115 #define CONFIG_CMD_IDE
116 #define CONFIG_CMD_NFS
117 #define CONFIG_CMD_SNTP
118 #define CONFIG_CMD_USB
119 #define CONFIG_CMD_MII
120 #define CONFIG_CMD_DHCP
121 #define CONFIG_CMD_PING
122 #define CONFIG_CMD_DISPLAY
124 #if defined(CONFIG_PCI)
125 #define CONFIG_CMD_PCI
128 #if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
129 #define CONFIG_SYS_LOWBOOT 1
130 #define CONFIG_SYS_LOWBOOT32 1
136 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
138 #define CONFIG_SYS_AUTOLOAD "n"
140 #define CONFIG_AUTOBOOT_KEYED
141 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
142 #define CONFIG_AUTOBOOT_DELAY_STR "asdfg"
144 #undef CONFIG_BOOTARGS
145 #define CONFIG_PREBOOT "run try_update"
147 #define CONFIG_EXTRA_ENV_SETTINGS \
148 "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
149 "cf1=diskboot 200000 0:1\0" \
150 "bootcmd_cf1=run bcf1\0" \
151 "bcf=setenv bootargs root=/dev/hda3\0" \
152 "bootcmd_nfs=run bnfs\0" \
153 "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs\0" \
154 "bootcmd_nor=cp.b ${kernel_addr} 200000 100000; run norargs addip; run bk\0" \
155 "bnfs=nfs 200000 ${rootpath}/boot/uImage ; run nfsargs addip ; run bk\0" \
156 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
157 "try_update=usb start;sleep 2;usb start;sleep 1;fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;source 2F0000\0" \
158 "env_addr=FE060000\0" \
159 "kernel_addr=FE100000\0" \
160 "rootfs_addr=FE200000\0" \
161 "add_mtd=setenv bootargs ${bootargs} mtdparts=phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
162 "bcf1=run cf1; run bcf; run addip; run bk\0" \
163 "add_consolespec=setenv bootargs ${bootargs} console=/dev/null quiet\0" \
164 "addip=if test \"${ethaddr}\" != \"00:00:00:00:00:00\" ; then if test -n ${ipaddr}; then setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1; fi ; fi\0" \
166 "ethaddr=00:00:00:00:00:00\0" \
168 "bootcmd=run bootcmd_nor\0" \
171 * IPB Bus clocking configuration.
173 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
178 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
179 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
181 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
182 #define CONFIG_SYS_I2C_SLAVE 0x7F
185 * EEPROM configuration
187 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */
188 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
189 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
190 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
191 #define CONFIG_SYS_EEPROM_WREN 1
192 #define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4
195 * Flash configuration
197 #define CONFIG_SYS_FLASH_BASE 0xFE000000
198 #define CONFIG_SYS_FLASH_SIZE 0x02000000
199 #if !defined(CONFIG_SYS_LOWBOOT)
200 #error "CONFIG_SYS_LOWBOOT not defined?"
201 #else /* CONFIG_SYS_LOWBOOT */
202 #if defined(CONFIG_SYS_LOWBOOT32)
203 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
205 #endif /* CONFIG_SYS_LOWBOOT */
207 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
208 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
209 #define CONFIG_FLASH_CFI_DRIVER
210 #define CONFIG_SYS_FLASH_CFI
211 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
212 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START}
215 * Environment settings
217 #define CONFIG_ENV_IS_IN_FLASH 1
218 #define CONFIG_ENV_SIZE 0x10000
219 #define CONFIG_ENV_SECT_SIZE 0x20000
220 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
221 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
223 #define CONFIG_ENV_OVERWRITE 1
228 #define CONFIG_SYS_MBAR 0xF0000000
229 #define CONFIG_SYS_SDRAM_BASE 0x00000000
230 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
232 /* Use SRAM until RAM will be available */
233 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
234 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
237 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
238 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
239 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
241 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
242 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
243 # define CONFIG_SYS_RAMBOOT 1
246 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
247 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
248 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
251 * Ethernet configuration
253 #define CONFIG_MPC5xxx_FEC 1
254 #define CONFIG_MPC5xxx_FEC_MII100
256 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
258 /* #define CONFIG_MPC5xxx_FEC_MII10 */
259 #define CONFIG_PHY_ADDR 0x1f
260 #define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */
265 #define CONFIG_SYS_GPS_PORT_CONFIG 0x18000004
268 * Miscellaneous configurable options
270 #define CONFIG_SYS_HUSH_PARSER
271 #define CONFIG_CMDLINE_EDITING 1
272 #ifdef CONFIG_SYS_HUSH_PARSER
273 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
275 #define CONFIG_SYS_LONGHELP /* undef to save memory */
276 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
277 #if defined(CONFIG_CMD_KGDB)
278 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
280 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
282 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
283 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
284 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
286 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
287 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
289 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
291 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
293 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
294 #if defined(CONFIG_CMD_KGDB)
295 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
300 * Various low-level settings
302 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
303 #define CONFIG_SYS_HID0_FINAL HID0_ICE
304 /* Flash at CSBoot, CS0 */
305 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
306 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
307 #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
308 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
309 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
310 /* External SRAM at CS1 */
311 #define CONFIG_SYS_CS1_START 0x62000000
312 #define CONFIG_SYS_CS1_SIZE 0x00400000
313 #define CONFIG_SYS_CS1_CFG 0x00009930
314 #define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START
315 #define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
316 /* LED display at CS7 */
317 #define CONFIG_SYS_CS7_START 0x6a000000
318 #define CONFIG_SYS_CS7_SIZE (64*1024)
319 #define CONFIG_SYS_CS7_CFG 0x0000bf30
321 #define CONFIG_SYS_CS_BURST 0x00000000
322 #define CONFIG_SYS_CS_DEADCYCLE 0x33333003
324 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
326 /*-----------------------------------------------------------------------
328 *-----------------------------------------------------------------------
330 #define CONFIG_USB_CLOCK 0x0001BBBB
331 #define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */
333 /*-----------------------------------------------------------------------
334 * IDE/ATA stuff Supports IDE harddisk
335 *-----------------------------------------------------------------------
338 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
340 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
341 #undef CONFIG_IDE_LED /* LED for ide not supported */
343 #define CONFIG_IDE_PREINIT
345 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
346 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
348 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
350 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
352 /* Offset for data I/O */
353 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
355 /* Offset for normal register accesses */
356 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
358 /* Offset for alternate registers */
359 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
361 /* Interval between registers */
362 #define CONFIG_SYS_ATA_STRIDE 4
364 #define CONFIG_ATAPI 1
366 /*-----------------------------------------------------------------------
367 * Open firmware flat tree support
368 *-----------------------------------------------------------------------
370 #define CONFIG_OF_LIBFDT 1
371 #define CONFIG_OF_BOARD_SETUP 1
373 #define OF_CPU "PowerPC,5200@0"
374 #define OF_SOC "soc5200@f0000000"
375 #define OF_TBCLK (bd->bi_busfreq / 4)
376 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
378 /* Support for the 7-segment display */
379 #define CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_CS7_START
380 #define CONFIG_SHOW_ACTIVITY /* used for display realization */
382 #define CONFIG_SHOW_BOOT_PROGRESS
384 #endif /* __CONFIG_H */