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x86: Remove CONFIG_SYS_EARLY_PCI_INIT
[u-boot] / include / configs / ac14xx.h
1 /*
2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3  * (C) Copyright 2010 DAVE Srl <www.dave.eu>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /*
9  * ifm AC14xx (MPC5121e based) board configuration file
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 #define CONFIG_AC14XX 1
16 #define CONFIG_DISPLAY_BOARDINFO
17
18 /*
19  * Memory map for the ifm AC14xx board:
20  *
21  * 0x0000_0000-0x0FFF_FFFF      DDR RAM (256 MB)
22  * 0x3000_0000-0x3001_FFFF      On Chip SRAM (128 KB)
23  * 0x8000_0000-0x803F_FFFF      IMMR (4 MB)
24  * 0xE000_0000-0xEFFF_FFFF      several LPB attached hardware (CSx)
25  * 0xFC00_0000-0xFFFF_FFFF      NOR Boot FLASH (64 MB)
26  */
27
28 /*
29  * High Level Configuration Options
30  */
31 #define CONFIG_E300             1       /* E300 Family */
32
33 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
34
35 #if defined(CONFIG_VIDEO)
36 #define CONFIG_CFB_CONSOLE
37 #define CONFIG_VGA_AS_SINGLE_DEVICE
38 #endif
39
40 #define CONFIG_SYS_MPC512X_CLKIN        25000000        /* in Hz */
41 #define SCFR1_IPS_DIV                   2
42 #define SCFR1_LPC_DIV                   2
43 #define SCFR1_NFC_DIV                   2
44 #define SCFR1_DIU_DIV                   240
45
46 #define CONFIG_MISC_INIT_R
47
48 #define CONFIG_SYS_IMMR                 0x80000000
49 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR + 0x2100)
50
51 /* more aggressive 'mtest' over a wider address range */
52 #define CONFIG_SYS_ALT_MEMTEST
53 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest region */
54 #define CONFIG_SYS_MEMTEST_END          0x0FE00000
55
56 /*
57  * DDR Setup - manually set all parameters as there's no SPD etc.
58  */
59 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
60 #define CONFIG_SYS_DDR_BASE             0x00000000
61 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
62 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
63
64 /*
65  * DDR Controller Configuration
66  *
67  * SYS_CFG:
68  *      [31:31] MDDRC Soft Reset:       Diabled
69  *      [30:30] DRAM CKE pin:           Enabled
70  *      [29:29] DRAM CLK:               Enabled
71  *      [28:28] Command Mode:           Enabled (For initialization only)
72  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
73  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
74  *      [20:19] Read Test:              DON'T USE
75  *      [18:18] Self Refresh:           Enabled
76  *      [17:17] 16bit Mode:             Disabled
77  *      [16:13] Ready Delay:            2
78  *      [12:12] Half DQS Delay:         Disabled
79  *      [11:11] Quarter DQS Delay:      Disabled
80  *      [10:08] Write Delay:            2
81  *      [07:07] Early ODT:              Disabled
82  *      [06:06] On DIE Termination:     Disabled
83  *      [05:05] FIFO Overflow Clear:    DON'T USE here
84  *      [04:04] FIFO Underflow Clear:   DON'T USE here
85  *      [03:03] FIFO Overflow Pending:  DON'T USE here
86  *      [02:02] FIFO Underlfow Pending: DON'T USE here
87  *      [01:01] FIFO Overlfow Enabled:  Enabled
88  *      [00:00] FIFO Underflow Enabled: Enabled
89  * TIME_CFG0
90  *      [31:16] DRAM Refresh Time:      0 CSB clocks
91  *      [15:8]  DRAM Command Time:      0 CSB clocks
92  *      [07:00] DRAM Precharge Time:    0 CSB clocks
93  * TIME_CFG1
94  *      [31:26] DRAM tRFC:
95  *      [25:21] DRAM tWR1:
96  *      [20:17] DRAM tWRT1:
97  *      [16:11] DRAM tDRR:
98  *      [10:05] DRAM tRC:
99  *      [04:00] DRAM tRAS:
100  * TIME_CFG2
101  *      [31:28] DRAM tRCD:
102  *      [27:23] DRAM tFAW:
103  *      [22:19] DRAM tRTW1:
104  *      [18:15] DRAM tCCD:
105  *      [14:10] DRAM tRTP:
106  *      [09:05] DRAM tRP:
107  *      [04:00] DRAM tRPA
108  */
109
110 /*
111  * NOTE: although this board uses DDR1 only, the common source brings defaults
112  * for DDR2 init sequences, that's why we have to keep those here as well
113  */
114
115 /* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
116 #define CONFIG_SYS_IOCTRL_MUX_DDR       ((0 << 6) | (3 << 3) | (3 << 0))
117
118 #define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
119                         | (1 << 31)     /* RST_B */ \
120                         | (1 << 30)     /* CKE */ \
121                         | (1 << 29)     /* CLK_ON */ \
122                         | (0 << 28)     /* CMD_MODE */ \
123                         | (5 << 25)     /* DRAM_ROW_SELECT */ \
124                         | (5 << 21)     /* DRAM_BANK_SELECT */ \
125                         | (0 << 18)     /* SELF_REF_EN */ \
126                         | (0 << 17)     /* 16BIT_MODE */ \
127                         | (4 << 13)     /* RDLY */ \
128                         | (1 << 12)     /* HALF_DQS_DLY */ \
129                         | (0 << 11)     /* QUART_DQS_DLY */ \
130                         | (1 <<  8)     /* WDLY */ \
131                         | (0 <<  7)     /* EARLY_ODT */ \
132                         | (0 <<  6)     /* ON_DIE_TERMINATE */ \
133                         | (0 <<  5)     /* FIFO_OV_CLEAR */ \
134                         | (0 <<  4)     /* FIFO_UV_CLEAR */ \
135                         | (0 <<  1)     /* FIFO_OV_EN */ \
136                         | (0 <<  0)     /* FIFO_UV_EN */ \
137                         )
138
139 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x04E03124
140 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x30CA1147
141 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x32B10864
142
143 /* register address only, i.e. template without values */
144 #define CONFIG_SYS_MICRON_BMODE         0x01000000
145 #define CONFIG_SYS_MICRON_EMODE         0x01010000
146 #define CONFIG_SYS_MICRON_EMODE2        0x01020000
147 #define CONFIG_SYS_MICRON_EMODE3        0x01030000
148 /*
149  * values for mode registers (without mode register address)
150  */
151 /* CAS 2.5 (6), burst seq (0) and length 4 (2) */
152 #define CONFIG_SYS_MICRON_BMODE_PARAM   0x00000062
153 #define CONFIG_SYS_MICRON_BMODE_RSTDLL  0x00000100
154 /* DLL enable, reduced drive strength */
155 #define CONFIG_SYS_MICRON_EMODE_PARAM   0x00000002
156
157 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
158 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
159 #define CONFIG_SYS_MICRON_EMR          ((1 << 24) |     /* CMD_REQ */ \
160                                         (0 << 22) |     /* DRAM_CS */ \
161                                         (0 << 21) |     /* DRAM_RAS */ \
162                                         (0 << 20) |     /* DRAM_CAS */ \
163                                         (0 << 19) |     /* DRAM_WEB */ \
164                                         (1 << 16) |     /* DRAM_BS[2:0] */ \
165                                         (0 << 15) |     /* */ \
166                                         (0 << 12) |     /* A12->out */ \
167                                         (0 << 11) |     /* A11->RDQS */ \
168                                         (0 << 10) |     /* A10->DQS# */ \
169                                         (0 <<  7) |     /* OCD program */ \
170                                         (0 <<  6) |     /* Rtt1 */ \
171                                         (0 <<  3) |     /* posted CAS# */ \
172                                         (0 <<  2) |     /* Rtt0 */ \
173                                         (1 <<  1) |     /* ODS */ \
174                                         (0 <<  0)       /* DLL */ \
175                                      )
176 #define CONFIG_SYS_MICRON_EMR2          0x01020000
177 #define CONFIG_SYS_MICRON_EMR3          0x01030000
178 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
179 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
180 #define CONFIG_SYS_MICRON_EMR_OCD      ((1 << 24) |     /* CMD_REQ */ \
181                                         (0 << 22) |     /* DRAM_CS */ \
182                                         (0 << 21) |     /* DRAM_RAS */ \
183                                         (0 << 20) |     /* DRAM_CAS */ \
184                                         (0 << 19) |     /* DRAM_WEB */ \
185                                         (1 << 16) |     /* DRAM_BS[2:0] */ \
186                                         (0 << 15) |     /* */ \
187                                         (0 << 12) |     /* A12->out */ \
188                                         (0 << 11) |     /* A11->RDQS */ \
189                                         (1 << 10) |     /* A10->DQS# */ \
190                                         (7 <<  7) |     /* OCD program */ \
191                                         (0 <<  6) |     /* Rtt1 */ \
192                                         (0 <<  3) |     /* posted CAS# */ \
193                                         (1 <<  2) |     /* Rtt0 */ \
194                                         (0 <<  1) |     /* ODS */ \
195                                         (0 <<  0)       /* DLL */ \
196                                      )
197
198 /*
199  * Backward compatible definitions,
200  * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
201  */
202 #define CONFIG_SYS_DDRCMD_EM2           (CONFIG_SYS_MICRON_EMR2)
203 #define CONFIG_SYS_DDRCMD_EM3           (CONFIG_SYS_MICRON_EMR3)
204 #define CONFIG_SYS_DDRCMD_EN_DLL        (CONFIG_SYS_MICRON_EMR)
205 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   (CONFIG_SYS_MICRON_EMR_OCD)
206
207 /* DDR Priority Manager Configuration */
208 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
209 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
210 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
211 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
212 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
213 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
214 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
215 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
216 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
217 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
218 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
219 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
220 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
221 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
222 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
223 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
224 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
225 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
226 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
227 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
228 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
229 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
230 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
231
232 /*
233  * NOR FLASH on the Local Bus
234  */
235 #define CONFIG_SYS_FLASH_CFI                            /* use the CFI code */
236 #define CONFIG_FLASH_CFI_DRIVER                         /* use the CFI driver */
237 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of FLASH */
238 #define CONFIG_SYS_FLASH_SIZE           0x04000000      /* max flash size */
239
240 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
241 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
242 #define CONFIG_SYS_FLASH_BANKS_LIST     { \
243         CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
244         }
245 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
246
247 #undef CONFIG_SYS_FLASH_CHECKSUM
248 #define CONFIG_SYS_FLASH_PROTECTION
249
250 /*
251  * SRAM support
252  */
253 #define CONFIG_SYS_SRAM_BASE            0x30000000
254 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
255
256 /*
257  * CS related parameters
258  */
259 /* CS0 Flash */
260 #define CONFIG_SYS_CS0_CFG              0x00031110
261 #define CONFIG_SYS_CS0_START            0xFC000000
262 #define CONFIG_SYS_CS0_SIZE             0x04000000
263 /* CS1 FRAM */
264 #define CONFIG_SYS_CS1_CFG              0x00011000
265 #define CONFIG_SYS_CS1_START            0xE0000000
266 #define CONFIG_SYS_CS1_SIZE             0x00010000
267 /* CS2 AS-i 1 */
268 #define CONFIG_SYS_CS2_CFG              0x00009100
269 #define CONFIG_SYS_CS2_START            0xE0100000
270 #define CONFIG_SYS_CS2_SIZE             0x00080000
271 /* CS3 netX */
272 #define CONFIG_SYS_CS3_CFG              0x000A1140
273 #define CONFIG_SYS_CS3_START            0xE0300000
274 #define CONFIG_SYS_CS3_SIZE             0x00020000
275 /* CS5 safety */
276 #define CONFIG_SYS_CS5_CFG              0x0011F000
277 #define CONFIG_SYS_CS5_START            0xE0400000
278 #define CONFIG_SYS_CS5_SIZE             0x00010000
279 /* CS6 AS-i 2 */
280 #define CONFIG_SYS_CS6_CFG              0x00009100
281 #define CONFIG_SYS_CS6_START            0xE0200000
282 #define CONFIG_SYS_CS6_SIZE             0x00080000
283
284 /* Don't use alternative CS timing for any CS */
285 #define CONFIG_SYS_CS_ALETIMING         0x00000000
286 #define CONFIG_SYS_CS_BURST             0x00000000
287 #define CONFIG_SYS_CS_DEADCYCLE         0x00000020
288 #define CONFIG_SYS_CS_HOLDCYCLE         0x00000020
289
290 /* Use SRAM for initial stack */
291 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE
292 #define CONFIG_SYS_INIT_RAM_END         CONFIG_SYS_SRAM_SIZE
293
294 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - \
295                                          GENERATED_GBL_DATA_SIZE)
296 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
297
298 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
299 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
300
301 #ifdef  CONFIG_FSL_DIU_FB
302 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)
303 #else
304 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
305 #endif
306
307 /*
308  * Serial Port
309  */
310 #define CONFIG_CONS_INDEX               1
311
312 /*
313  * Serial console configuration
314  */
315 #define CONFIG_PSC_CONSOLE              3       /* console on PSC3 */
316 #define CONFIG_SYS_PSC3
317 #if CONFIG_PSC_CONSOLE != 3
318 #error CONFIG_PSC_CONSOLE must be 3
319 #endif
320
321 #define CONFIG_BAUDRATE                 115200  /* ... at 115200 bps */
322
323 #define CONSOLE_FIFO_TX_SIZE            FIFOC_PSC3_TX_SIZE
324 #define CONSOLE_FIFO_TX_ADDR            FIFOC_PSC3_TX_ADDR
325 #define CONSOLE_FIFO_RX_SIZE            FIFOC_PSC3_RX_SIZE
326 #define CONSOLE_FIFO_RX_ADDR            FIFOC_PSC3_RX_ADDR
327
328 /*
329  * Clocks in use
330  */
331 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |           \
332                          CLOCK_SCCR1_LPC_EN |           \
333                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
334                          CLOCK_SCCR1_PSC_EN(7) |        \
335                          CLOCK_SCCR1_PSCFIFO_EN |       \
336                          CLOCK_SCCR1_DDR_EN |           \
337                          CLOCK_SCCR1_FEC_EN |           \
338                          CLOCK_SCCR1_TPR_EN)
339
340 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
341                          CLOCK_SCCR2_SPDIF_EN |         \
342                          CLOCK_SCCR2_DIU_EN |           \
343                          CLOCK_SCCR2_I2C_EN)
344
345
346 #define CONFIG_CMDLINE_EDITING          1       /* command line history */
347
348 /* I2C */
349 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
350 #define CONFIG_I2C_MULTI_BUS
351
352 /* I2C speed and slave address */
353 #define CONFIG_SYS_I2C_SPEED            100000
354 #define CONFIG_SYS_I2C_SLAVE            0x7F
355
356 /*
357  * IIM - IC Identification Module
358  */
359 #undef CONFIG_FSL_IIM
360
361 /*
362  * EEPROM configuration for Atmel AT24C01:
363  * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
364  */
365 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
366 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x52
367 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   30
368 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
369
370 /*
371  * Ethernet configuration
372  */
373 #define CONFIG_MPC512x_FEC              1
374 #define CONFIG_PHY_ADDR                 0x1F
375 #define CONFIG_MII                      1       /* MII PHY management */
376 #define CONFIG_FEC_AN_TIMEOUT           1
377 #define CONFIG_HAS_ETH0
378
379 /*
380  * Environment
381  */
382 #define CONFIG_ENV_IS_IN_FLASH          1
383 /* This has to be a multiple of the flash sector size */
384 #define CONFIG_ENV_ADDR                 0xFFF40000
385 #define CONFIG_ENV_SIZE                 0x2000
386 #define CONFIG_ENV_SECT_SIZE            0x20000
387
388 /* Address and size of Redundant Environment Sector */
389 #define CONFIG_ENV_ADDR_REDUND          (CONFIG_ENV_ADDR + \
390                                          CONFIG_ENV_SECT_SIZE)
391 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
392
393 #define CONFIG_LOADS_ECHO               1
394 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1
395
396 #define CONFIG_CMD_ASKENV
397 #define CONFIG_CMD_DHCP
398 #define CONFIG_CMD_EEPROM
399 #undef CONFIG_CMD_FUSE
400 #define CONFIG_CMD_I2C
401 #undef CONFIG_CMD_IDE
402 #undef CONFIG_CMD_EXT2
403 #define CONFIG_CMD_JFFS2
404 #define CONFIG_CMD_MII
405 #define CONFIG_CMD_PING
406 #define CONFIG_CMD_REGINFO
407
408 #if defined(CONFIG_PCI)
409 #define CONFIG_CMD_PCI
410 #endif
411
412 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
413 #define CONFIG_DOS_PARTITION
414 #define CONFIG_MAC_PARTITION
415 #define CONFIG_ISO_PARTITION
416 #endif /* defined(CONFIG_CMD_IDE) */
417
418 /*
419  * Miscellaneous configurable options
420  */
421 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
422 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
423
424 #ifdef CONFIG_CMD_KGDB
425 # define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
426 #else
427 # define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
428 #endif
429
430 /* Print Buffer Size */
431 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
432                                  sizeof(CONFIG_SYS_PROMPT) + 16)
433 /* max number of command args */
434 #define CONFIG_SYS_MAXARGS      32
435 /* Boot Argument Buffer Size */
436 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
437
438 /*
439  * For booting Linux, the board info and command line data
440  * have to be in the first 8 MB of memory, since this is
441  * the maximum mapped by the Linux kernel during initialization.
442  */
443 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
444
445 /* Cache Configuration */
446 #define CONFIG_SYS_DCACHE_SIZE          32768
447 #define CONFIG_SYS_CACHELINE_SIZE       32
448 #ifdef CONFIG_CMD_KGDB
449 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of 32 */
450 #endif
451
452 #define CONFIG_SYS_HID0_INIT            0x000000000
453 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
454                                          HID0_ICE)
455 #define CONFIG_SYS_HID2 HID2_HBE
456
457 #define CONFIG_HIGH_BATS                1       /* High BATs supported */
458
459 /*
460  * Internal Definitions
461  *
462  * Boot Flags
463  */
464 #define BOOTFLAG_COLD                   0x01
465 #define BOOTFLAG_WARM                   0x02
466
467 #ifdef CONFIG_CMD_KGDB
468 #define CONFIG_KGDB_BAUDRATE            230400  /* speed of kgdb serial port */
469 #endif
470
471 /*
472  * Environment Configuration
473  */
474 #define CONFIG_ENV_OVERWRITE
475 #define CONFIG_TIMESTAMP
476
477 /* default load addr for tftp and bootm */
478 #define CONFIG_LOADADDR         400000
479
480 #define CONFIG_BOOTDELAY        2       /* -1 disables auto-boot */
481
482 /* the builtin environment and standard greeting */
483 #define CONFIG_PREBOOT  "echo;" \
484         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
485         "echo"
486
487 #define CONFIG_EXTRA_ENV_SETTINGS_DEVEL                                 \
488         "muster_nr=-00\0"                                               \
489         "fromram=run ramargs addip addtty; "                            \
490                 "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "    \
491                 "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "     \
492                 "tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; "       \
493                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
494         "fromnfs=run nfsargs addip addtty; "                            \
495                 "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "    \
496                 "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "     \
497                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
498         "fromflash=run nfsargs addip addtty; "                          \
499                 "bootm fc020000 - fc000000\0"                           \
500         "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0"           \
501         "recovery=run mtdargsrec addip addtty; "                        \
502                 "bootm ffd20000 - ffee0000\0"                           \
503         "production=run ramargs addip addtty; "                         \
504                 "bootm fc020000 fc400000 fc000000\0"                    \
505         "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0"              \
506         "prodmtd=run mtdargs addip addtty; "                            \
507                 "bootm fc020000 - fc000000\0"                           \
508         ""
509
510 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
511         "u-boot_addr_r=200000\0"                                        \
512         "kernel_addr_r=600000\0"                                        \
513         "fdt_addr_r=a00000\0"                                           \
514         "ramdisk_addr_r=b00000\0"                                       \
515         "u-boot_addr=FFF00000\0"                                        \
516         "kernel_addr=FC020000\0"                                        \
517         "fdt_addr=FC000000\0"                                           \
518         "ramdisk_addr=FC400000\0"                                       \
519         "verify=n\0"                                                    \
520         "ramdiskfile=ac14xx/uRamdisk\0"                                 \
521         "u-boot=ac14xx/u-boot.bin\0"                                    \
522         "bootfile=ac14xx/uImage\0"                                      \
523         "fdtfile=ac14xx/ac14xx.dtb\0"                                   \
524         "netdev=eth0\0"                                                 \
525         "consdev=ttyPSC0\0"                                             \
526         "hostname=ac14xx\0"                                             \
527         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
528                 "nfsroot=${serverip}:${rootpath}${muster_nr}\0" \
529         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
530         "addip=setenv bootargs ${bootargs} "                            \
531                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
532                 ":${hostname}:${netdev}:off panic=1\0"                  \
533         "addtty=setenv bootargs ${bootargs} "                           \
534                 "console=${consdev},${baudrate}\0"                      \
535         "flash_nfs=run nfsargs addip addtty;"                           \
536                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
537         "flash_self=run ramargs addip addtty;"                          \
538                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
539         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
540                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
541                 "run nfsargs addip addtty;"                             \
542                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
543         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
544                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
545                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
546                 "run ramargs addip addtty;"                             \
547                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
548         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
549         "update=protect off ${u-boot_addr} +${filesize};"               \
550                 "era ${u-boot_addr} +${filesize};"                      \
551                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
552         CONFIG_EXTRA_ENV_SETTINGS_DEVEL                                 \
553         "upd=run load update\0"                                         \
554         ""
555
556 #define CONFIG_BOOTCOMMAND      "run production"
557
558 #define CONFIG_ARP_TIMEOUT      200UL
559
560 #define CONFIG_FIT              1
561 #define CONFIG_OF_LIBFDT        1
562 #define CONFIG_OF_BOARD_SETUP   1
563 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
564
565 #define OF_CPU                  "PowerPC,5121@0"
566 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
567 #define OF_TBCLK                (bd->bi_busfreq / 4)
568 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
569
570 #endif  /* __CONFIG_H */