3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 /************************************************************************
9 * acadia.h - configuration for AMCC Acadia (405EZ)
10 ***********************************************************************/
15 /*-----------------------------------------------------------------------
16 * High Level Configuration Options
17 *----------------------------------------------------------------------*/
18 #define CONFIG_ACADIA 1 /* Board is Acadia */
19 #define CONFIG_405EZ 1 /* Specifc 405EZ support*/
21 #ifndef CONFIG_SYS_TEXT_BASE
22 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
26 * Include common defines/options for all AMCC eval boards
28 #define CONFIG_HOSTNAME acadia
29 #include "amcc-common.h"
31 /* Detect Acadia PLL input clock automatically via CPLD bit */
32 #define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
35 #define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
37 #define CONFIG_NO_SERIAL_EEPROM
38 /*#undef CONFIG_NO_SERIAL_EEPROM*/
40 #ifdef CONFIG_NO_SERIAL_EEPROM
41 /*----------------------------------------------------------------------------
42 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
43 * assuming a 66MHz input clock to the 405EZ.
44 *---------------------------------------------------------------------------*/
45 /* #define PLLMR0_100_100_12 */
46 #define PLLMR0_200_133_66
47 /* #define PLLMR0_266_160_80 */
48 /* #define PLLMR0_333_166_83 */
51 /*-----------------------------------------------------------------------
52 * Base addresses -- Note these are effective addresses where the
53 * actual resources get mapped (not physical addresses)
54 *----------------------------------------------------------------------*/
55 #define CONFIG_SYS_FLASH_BASE 0xfe000000
56 #define CONFIG_SYS_CPLD_BASE 0x80000000
57 #define CONFIG_SYS_NAND_ADDR 0xd0000000
58 #define CONFIG_SYS_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
60 /*-----------------------------------------------------------------------
61 * Initial RAM & stack pointer
62 *----------------------------------------------------------------------*/
63 #define CONFIG_SYS_TEMP_STACK_OCM 1 /* OCM as init ram */
65 /* On Chip Memory location */
66 #define CONFIG_SYS_OCM_DATA_ADDR 0xf8000000
67 #define CONFIG_SYS_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
68 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SRAM */
69 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
71 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
72 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
74 /*-----------------------------------------------------------------------
76 *----------------------------------------------------------------------*/
77 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
78 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
79 #define CONFIG_SYS_BASE_BAUD 691200
81 /*-----------------------------------------------------------------------
83 *----------------------------------------------------------------------*/
84 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
86 /*-----------------------------------------------------------------------
88 *----------------------------------------------------------------------*/
89 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
90 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
92 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
93 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
94 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
96 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
97 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
99 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
100 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
102 #ifdef CONFIG_ENV_IS_IN_FLASH
103 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
104 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
105 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
107 /* Address and size of Redundant Environment Sector */
108 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
109 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
112 /*-----------------------------------------------------------------------
114 *----------------------------------------------------------------------*/
115 #define CONFIG_SYS_MBYTES_RAM 64 /* 64MB */
117 /*-----------------------------------------------------------------------
119 *----------------------------------------------------------------------*/
120 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
122 #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
123 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
125 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
127 /*-----------------------------------------------------------------------
129 *----------------------------------------------------------------------*/
130 #define CONFIG_PHY_ADDR 0 /* PHY address */
131 #define CONFIG_HAS_ETH0 1
134 * Default environment variables
136 #define CONFIG_EXTRA_ENV_SETTINGS \
137 CONFIG_AMCC_DEF_ENV \
138 CONFIG_AMCC_DEF_ENV_POWERPC \
139 CONFIG_AMCC_DEF_ENV_PPC_OLD \
140 CONFIG_AMCC_DEF_ENV_NOR_UPD \
141 "kernel_addr=fff10000\0" \
142 "ramdisk_addr=fff20000\0" \
143 "kozio=bootm ffc60000\0" \
146 #define CONFIG_USB_OHCI
150 #define CONFIG_SUPPORT_VFAT
153 * Commands additional to the ones defined in amcc-common.h
155 #define CONFIG_CMD_NAND
157 /*-----------------------------------------------------------------------
159 *----------------------------------------------------------------------*/
160 #define CONFIG_SYS_MAX_NAND_DEVICE 1
161 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
162 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
164 /*-----------------------------------------------------------------------
165 * External Bus Controller (EBC) Setup
166 *----------------------------------------------------------------------*/
167 #define CONFIG_SYS_NAND_CS 3
168 /* Memory Bank 0 (Flash) initialization */
169 #define CONFIG_SYS_EBC_PB0AP 0x03337200
170 #define CONFIG_SYS_EBC_PB0CR 0xfe0bc000
172 /* Memory Bank 3 (NAND-FLASH) initialization */
173 #define CONFIG_SYS_EBC_PB3AP 0x018003c0
174 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
176 /* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
177 /* Memory Bank 1 (CRAM) initialization */
178 #define CONFIG_SYS_EBC_PB1AP 0x030400c0
179 #define CONFIG_SYS_EBC_PB1CR 0x000bc000
181 /* Memory Bank 2 (CRAM) initialization */
182 #define CONFIG_SYS_EBC_PB2AP 0x030400c0
183 #define CONFIG_SYS_EBC_PB2CR 0x020bc000
185 /* Memory Bank 4 (CPLD) initialization */
186 #define CONFIG_SYS_EBC_PB4AP 0x04006000
187 #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CPLD_BASE | 0x18000)
189 #define CONFIG_SYS_EBC_CFG 0xf8400000
191 /*-----------------------------------------------------------------------
193 *----------------------------------------------------------------------*/
194 #define CONFIG_SYS_GPIO_CRAM_CLK 8
195 #define CONFIG_SYS_GPIO_CRAM_WAIT 9 /* GPIO-In */
196 #define CONFIG_SYS_GPIO_CRAM_ADV 10
197 #define CONFIG_SYS_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
199 /*-----------------------------------------------------------------------
200 * Definitions for GPIO_0 setup (PPC405EZ specific)
202 * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
203 * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
204 * GPIO0[4] - External Bus Controller Hold Input
205 * GPIO0[5] - External Bus Controller Priority Input
206 * GPIO0[6] - External Bus Controller HLDA Output
207 * GPIO0[7] - External Bus Controller Bus Request Output
208 * GPIO0[8] - CRAM Clk Output
209 * GPIO0[9] - External Bus Controller Ready Input
210 * GPIO0[10] - CRAM Adv Output
211 * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
212 * GPIO0[25] - External DMA Request Input
213 * GPIO0[26] - External DMA EOT I/O
214 * GPIO0[25] - External DMA Ack_n Output
215 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
216 * GPIO0[28-30] - Trace Outputs / PWM Inputs
217 * GPIO0[31] - PWM_8 I/O
219 #define CONFIG_SYS_GPIO0_TCR 0xC0A00000
220 #define CONFIG_SYS_GPIO0_OSRL 0x50004400
221 #define CONFIG_SYS_GPIO0_OSRH 0x02000055
222 #define CONFIG_SYS_GPIO0_ISR1L 0x00001000
223 #define CONFIG_SYS_GPIO0_ISR1H 0x00000055
224 #define CONFIG_SYS_GPIO0_TSRL 0x02000000
225 #define CONFIG_SYS_GPIO0_TSRH 0x00000055
227 /*-----------------------------------------------------------------------
228 * Definitions for GPIO_1 setup (PPC405EZ specific)
230 * GPIO1[0-6] - PWM_9 to PWM_15 I/O
231 * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
232 * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
233 * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
234 * GPIO1[10-12] - UART0 Control Inputs
235 * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
236 * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
237 * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
238 * GPIO1[16] - SPI_SS_1_N Output
239 * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
241 #define CONFIG_SYS_GPIO1_TCR 0xFFFF8414
242 #define CONFIG_SYS_GPIO1_OSRL 0x40000110
243 #define CONFIG_SYS_GPIO1_OSRH 0x55455555
244 #define CONFIG_SYS_GPIO1_ISR1L 0x15555445
245 #define CONFIG_SYS_GPIO1_ISR1H 0x00000000
246 #define CONFIG_SYS_GPIO1_TSRL 0x00000000
247 #define CONFIG_SYS_GPIO1_TSRH 0x00000000
249 #endif /* __CONFIG_H */