git.sur5r.net Git - u-boot/blob - include/configs/acadia.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /************************************************************************
   9  * acadia.h - configuration for AMCC Acadia (405EZ)
  10  ***********************************************************************/
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*-----------------------------------------------------------------------
  16  * High Level Configuration Options
  17  *----------------------------------------------------------------------*/
  18 #define CONFIG_ACADIA           1               /* Board is Acadia      */
  19 #define CONFIG_405EZ            1               /* Specifc 405EZ support*/
  20
  21 #ifndef CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  23 #endif
  24
  25 /*
  26  * Include common defines/options for all AMCC eval boards
  27  */
  28 #define CONFIG_HOSTNAME         acadia
  29 #include "amcc-common.h"
  30
  31 /* Detect Acadia PLL input clock automatically via CPLD bit             */
  32 #define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
  33                                 66666666 : 33333000)
  34
  35 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  36 #define CONFIG_MISC_INIT_F      1               /* Call misc_init_f     */
  37
  38 #define CONFIG_NO_SERIAL_EEPROM
  39 /*#undef CONFIG_NO_SERIAL_EEPROM*/
  40
  41 #ifdef CONFIG_NO_SERIAL_EEPROM
  42 /*----------------------------------------------------------------------------
  43  * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  44  * assuming a 66MHz input clock to the 405EZ.
  45  *---------------------------------------------------------------------------*/
  46 /* #define PLLMR0_100_100_12 */
  47 #define PLLMR0_200_133_66
  48 /* #define PLLMR0_266_160_80 */
  49 /* #define PLLMR0_333_166_83 */
  50 #endif
  51
  52 /*-----------------------------------------------------------------------
  53  * Base addresses -- Note these are effective addresses where the
  54  * actual resources get mapped (not physical addresses)
  55  *----------------------------------------------------------------------*/
  56 #define CONFIG_SYS_FLASH_BASE           0xfe000000
  57 #define CONFIG_SYS_CPLD_BASE            0x80000000
  58 #define CONFIG_SYS_NAND_ADDR            0xd0000000
  59 #define CONFIG_SYS_USB_HOST             0xef603000      /* USB OHCI 1.1 controller      */
  60
  61 /*-----------------------------------------------------------------------
  62  * Initial RAM & stack pointer
  63  *----------------------------------------------------------------------*/
  64 #define CONFIG_SYS_TEMP_STACK_OCM       1               /* OCM as init ram      */
  65
  66 /* On Chip Memory location */
  67 #define CONFIG_SYS_OCM_DATA_ADDR        0xf8000000
  68 #define CONFIG_SYS_OCM_DATA_SIZE        0x4000                  /* 16K of onchip SRAM           */
  69 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of SRAM               */
  70 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of used area in RAM     */
  71
  72 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  73 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  74
  75 /*-----------------------------------------------------------------------
  76  * Serial Port
  77  *----------------------------------------------------------------------*/
  78 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  79 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK                     /* external serial clock */
  80 #define CONFIG_SYS_BASE_BAUD            691200
  81
  82 /*-----------------------------------------------------------------------
  83  * Environment
  84  *----------------------------------------------------------------------*/
  85 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  86
  87 /*-----------------------------------------------------------------------
  88  * FLASH related
  89  *----------------------------------------------------------------------*/
  90 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
  91 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
  92
  93 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
  94 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
  95 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
  96
  97 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
  98 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
  99
 100 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 101 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 102
 103 #ifdef CONFIG_ENV_IS_IN_FLASH
 104 #define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector  */
 105 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 106 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 107
 108 /* Address and size of Redundant Environment Sector     */
 109 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 110 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 111 #endif
 112
 113 /*-----------------------------------------------------------------------
 114  * RAM (CRAM)
 115  *----------------------------------------------------------------------*/
 116 #define CONFIG_SYS_MBYTES_RAM           64              /* 64MB                 */
 117
 118 /*-----------------------------------------------------------------------
 119  * I2C
 120  *----------------------------------------------------------------------*/
 121 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 122
 123 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 124 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 126 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 127 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 128
 129 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 130 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 131 #define CONFIG_DTT_AD7414       1               /* use AD7414           */
 132 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 133 #define CONFIG_SYS_DTT_MAX_TEMP 70
 134 #define CONFIG_SYS_DTT_LOW_TEMP -30
 135 #define CONFIG_SYS_DTT_HYSTERESIS       3
 136
 137 /*-----------------------------------------------------------------------
 138  * Ethernet
 139  *----------------------------------------------------------------------*/
 140 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
 141 #define CONFIG_HAS_ETH0         1
 142
 143 /*
 144  * Default environment variables
 145  */
 146 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 147         CONFIG_AMCC_DEF_ENV                                             \
 148         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 149         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 150         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 151         "kernel_addr=fff10000\0"                                        \
 152         "ramdisk_addr=fff20000\0"                                       \
 153         "kozio=bootm ffc60000\0"                                        \
 154         ""
 155
 156 #define CONFIG_USB_OHCI
 157 #define CONFIG_USB_STORAGE
 158
 159 /* Partitions */
 160 #define CONFIG_MAC_PARTITION
 161 #define CONFIG_DOS_PARTITION
 162 #define CONFIG_ISO_PARTITION
 163
 164 #define CONFIG_SUPPORT_VFAT
 165
 166 /*
 167  * Commands additional to the ones defined in amcc-common.h
 168  */
 169 #define CONFIG_CMD_DTT
 170 #define CONFIG_CMD_NAND
 171 #define CONFIG_CMD_USB
 172
 173 /*-----------------------------------------------------------------------
 174  * NAND FLASH
 175  *----------------------------------------------------------------------*/
 176 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 177 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 178 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 179
 180 /*-----------------------------------------------------------------------
 181  * External Bus Controller (EBC) Setup
 182  *----------------------------------------------------------------------*/
 183 #define CONFIG_SYS_NAND_CS              3
 184 /* Memory Bank 0 (Flash) initialization                                         */
 185 #define CONFIG_SYS_EBC_PB0AP            0x03337200
 186 #define CONFIG_SYS_EBC_PB0CR            0xfe0bc000
 187
 188 /* Memory Bank 3 (NAND-FLASH) initialization                                    */
 189 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 190 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 191
 192 /* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
 193 /* Memory Bank 1 (CRAM) initialization                                          */
 194 #define CONFIG_SYS_EBC_PB1AP            0x030400c0
 195 #define CONFIG_SYS_EBC_PB1CR            0x000bc000
 196
 197 /* Memory Bank 2 (CRAM) initialization                                          */
 198 #define CONFIG_SYS_EBC_PB2AP            0x030400c0
 199 #define CONFIG_SYS_EBC_PB2CR            0x020bc000
 200
 201 /* Memory Bank 4 (CPLD) initialization                                          */
 202 #define CONFIG_SYS_EBC_PB4AP            0x04006000
 203 #define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_CPLD_BASE | 0x18000)
 204
 205 #define CONFIG_SYS_EBC_CFG              0xf8400000
 206
 207 /*-----------------------------------------------------------------------
 208  * GPIO Setup
 209  *----------------------------------------------------------------------*/
 210 #define CONFIG_SYS_GPIO_CRAM_CLK        8
 211 #define CONFIG_SYS_GPIO_CRAM_WAIT       9               /* GPIO-In              */
 212 #define CONFIG_SYS_GPIO_CRAM_ADV        10
 213 #define CONFIG_SYS_GPIO_CRAM_CRE        (32 + 21)       /* GPIO-Out             */
 214
 215 /*-----------------------------------------------------------------------
 216  * Definitions for GPIO_0 setup (PPC405EZ specific)
 217  *
 218  * GPIO0[0-2]   - External Bus Controller CS_4 - CS_6 Outputs
 219  * GPIO0[3]     - NAND FLASH Controller CE3 (NFCE3) Output
 220  * GPIO0[4]     - External Bus Controller Hold Input
 221  * GPIO0[5]     - External Bus Controller Priority Input
 222  * GPIO0[6]     - External Bus Controller HLDA Output
 223  * GPIO0[7]     - External Bus Controller Bus Request Output
 224  * GPIO0[8]     - CRAM Clk Output
 225  * GPIO0[9]     - External Bus Controller Ready Input
 226  * GPIO0[10]    - CRAM Adv Output
 227  * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
 228  * GPIO0[25]    - External DMA Request Input
 229  * GPIO0[26]    - External DMA EOT I/O
 230  * GPIO0[25]    - External DMA Ack_n Output
 231  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 232  * GPIO0[28-30] - Trace Outputs / PWM Inputs
 233  * GPIO0[31]    - PWM_8 I/O
 234  */
 235 #define CONFIG_SYS_GPIO0_TCR            0xC0A00000
 236 #define CONFIG_SYS_GPIO0_OSRL           0x50004400
 237 #define CONFIG_SYS_GPIO0_OSRH           0x02000055
 238 #define CONFIG_SYS_GPIO0_ISR1L          0x00001000
 239 #define CONFIG_SYS_GPIO0_ISR1H          0x00000055
 240 #define CONFIG_SYS_GPIO0_TSRL           0x02000000
 241 #define CONFIG_SYS_GPIO0_TSRH           0x00000055
 242
 243 /*-----------------------------------------------------------------------
 244  * Definitions for GPIO_1 setup (PPC405EZ specific)
 245  *
 246  * GPIO1[0-6]   - PWM_9 to PWM_15 I/O
 247  * GPIO1[7]     - PWM_DIV_CLK (Out) / IRQ4 Input
 248  * GPIO1[8]     - TS5 Output / DAC_IP_TRIG Input
 249  * GPIO1[9]     - TS6 Output / ADC_IP_TRIG Input
 250  * GPIO1[10-12] - UART0 Control Inputs
 251  * GPIO1[13]    - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
 252  * GPIO1[14]    - UART0_RTS_N Output/SPI_SS_2_N Output
 253  * GPIO1[15]    - SPI_SS_3_N Output/UART0_RI_N Input
 254  * GPIO1[16]    - SPI_SS_1_N Output
 255  * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
 256  */
 257 #define CONFIG_SYS_GPIO1_TCR            0xFFFF8414
 258 #define CONFIG_SYS_GPIO1_OSRL           0x40000110
 259 #define CONFIG_SYS_GPIO1_OSRH           0x55455555
 260 #define CONFIG_SYS_GPIO1_ISR1L          0x15555445
 261 #define CONFIG_SYS_GPIO1_ISR1H          0x00000000
 262 #define CONFIG_SYS_GPIO1_TSRL           0x00000000
 263 #define CONFIG_SYS_GPIO1_TSRH           0x00000000
 264
 265 #endif  /* __CONFIG_H */