2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/ag101.h>
15 * CPU and Board Configuration Options
17 #define CONFIG_ADP_AG101
19 #define CONFIG_USE_INTERRUPT
21 #define CONFIG_SKIP_LOWLEVEL_INIT
23 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
24 #define CONFIG_MEM_REMAP
27 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
28 #define CONFIG_SYS_TEXT_BASE 0x03200000
30 #define CONFIG_SYS_TEXT_BASE 0x00000000
38 * According to the discussion in u-boot mailing list before,
39 * CONFIG_SYS_HZ at 1000 is mandatory.
41 #define CONFIG_SYS_HZ 1000
42 #define CONFIG_SYS_CLK_FREQ 48000000
43 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
46 * Use Externel CLOCK or PCLK
48 #undef CONFIG_FTRTC010_EXTCLK
50 #ifndef CONFIG_FTRTC010_EXTCLK
51 #define CONFIG_FTRTC010_PCLK
54 #ifdef CONFIG_FTRTC010_EXTCLK
55 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
57 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
60 #define TIMER_LOAD_VAL 0xffffffff
65 #define CONFIG_RTC_FTRTC010
68 * Real Time Clock Divider
69 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
71 #define OSC_5MHZ (5*1000000)
72 #define OSC_CLK (2*OSC_5MHZ)
73 #define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
76 * Serial console configuration
79 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
80 #define CONFIG_BAUDRATE 38400
81 #define CONFIG_CONS_INDEX 1
82 #define CONFIG_SYS_NS16550
83 #define CONFIG_SYS_NS16550_SERIAL
84 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
85 #define CONFIG_SYS_NS16550_REG_SIZE -4
86 #define CONFIG_SYS_NS16550_CLK ((46080000 * 20) / 25) /* AG101 */
91 #define CONFIG_FTMAC100
93 #define CONFIG_BOOTDELAY 3
99 #define CONFIG_CMD_MMC
100 #define CONFIG_GENERIC_MMC
101 #define CONFIG_DOS_PARTITION
102 #define CONFIG_FTSDC010
103 #define CONFIG_FTSDC010_NUMBER 1
104 #define CONFIG_CMD_FAT
107 * Command line configuration.
109 #include <config_cmd_default.h>
111 #define CONFIG_CMD_CACHE
112 #define CONFIG_CMD_DATE
113 #define CONFIG_CMD_PING
116 * Miscellaneous configurable options
118 #define CONFIG_SYS_LONGHELP /* undef to save memory */
119 #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
120 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
122 /* Print Buffer Size */
123 #define CONFIG_SYS_PBSIZE \
124 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
126 /* max number of command args */
127 #define CONFIG_SYS_MAXARGS 16
129 /* Boot Argument Buffer Size */
130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
133 * Size of malloc() pool
135 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
136 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
139 * size in bytes reserved for initial data
141 #define CONFIG_SYS_GBL_DATA_SIZE 128
144 * AHB Controller configuration
146 #define CONFIG_FTAHBC020S
148 #ifdef CONFIG_FTAHBC020S
149 #include <faraday/ftahbc020s.h>
151 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
152 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
155 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
156 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
159 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
160 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
161 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
167 #define CONFIG_FTWDT010_WATCHDOG
170 * PMU Power controller configuration
173 #define CONFIG_FTPMU010_POWER
175 #ifdef CONFIG_FTPMU010_POWER
176 #include <faraday/ftpmu010.h>
177 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
178 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
179 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
180 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
181 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
182 FTPMU010_SDRAMHTC_CKE_DCSR | \
183 FTPMU010_SDRAMHTC_DQM_DCSR | \
184 FTPMU010_SDRAMHTC_SDCLK_DCSR)
188 * SDRAM controller configuration
190 #define CONFIG_FTSDMC021
192 #ifdef CONFIG_FTSDMC021
193 #include <faraday/ftsdmc021.h>
195 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRP(1) | \
196 FTSDMC021_TP1_TRCD(1) | \
197 FTSDMC021_TP1_TRF(3) | \
198 FTSDMC021_TP1_TWR(1) | \
199 FTSDMC021_TP1_TCL(2))
201 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
202 FTSDMC021_TP2_INI_REFT(8) | \
203 FTSDMC021_TP2_REF_INTV(0x180))
206 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
207 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
210 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
211 FTSDMC021_CR1_DSZ(3) | \
212 FTSDMC021_CR1_MBW(2) | \
213 FTSDMC021_CR1_BNKSIZE(6))
215 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
216 FTSDMC021_CR2_IREF | \
219 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
220 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
221 CONFIG_SYS_FTSDMC021_BANK0_BASE)
226 * Physical Memory Map
228 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
229 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
230 #if defined(CONFIG_MEM_REMAP)
231 #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/
233 #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
234 #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */
237 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
238 #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
240 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
242 #ifdef CONFIG_MEM_REMAP
243 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
244 GENERATED_GBL_DATA_SIZE)
246 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
247 GENERATED_GBL_DATA_SIZE)
248 #endif /* CONFIG_MEM_REMAP */
251 * Load address and memory test area should agree with
252 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
254 #define CONFIG_SYS_LOAD_ADDR 0x300000
256 /* memtest works on 63 MB in DRAM */
257 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
258 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
261 * Static memory controller configuration
263 #define CONFIG_FTSMC020
265 #ifdef CONFIG_FTSMC020
266 #include <faraday/ftsmc020.h>
268 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
269 #define CONFIG_SYS_FTSMC020_CONFIGS { \
270 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
271 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
274 #define CONFIG_SYS_FTSMC020_CONFIGS { \
275 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
280 * There are 2 bank connected to FTSMC020 on ADP-AG101.
281 * You can use jumper and switch to force it booted from ROM or FLASH.
282 * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
283 * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
285 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
286 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
287 FTSMC020_BANK_SIZE_32M | \
288 FTSMC020_BANK_MBW_32)
290 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
291 FTSMC020_TPR_AST(1) | \
292 FTSMC020_TPR_CTW(1) | \
293 FTSMC020_TPR_ATI(1) | \
294 FTSMC020_TPR_AT2(1) | \
295 FTSMC020_TPR_WTC(1) | \
296 FTSMC020_TPR_AHT(1) | \
297 FTSMC020_TPR_TRNA(1))
301 * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
302 * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
303 * Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
304 * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
306 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_SIZE_32M | \
307 FTSMC020_BANK_MBW_32)
309 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
310 FTSMC020_TPR_AST(3) | \
311 FTSMC020_TPR_CTW(3) | \
312 FTSMC020_TPR_ATI(0xf) | \
313 FTSMC020_TPR_AT2(3) | \
314 FTSMC020_TPR_WTC(3) | \
315 FTSMC020_TPR_AHT(3) | \
316 FTSMC020_TPR_TRNA(0xf))
318 #define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
319 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
320 FTSMC020_BANK_SIZE_32M | \
321 FTSMC020_BANK_MBW_32)
323 #define FTSMC020_BANK1_TIMING (FTSMC020_TPR_RBE | \
324 FTSMC020_TPR_AST(1) | \
325 FTSMC020_TPR_CTW(1) | \
326 FTSMC020_TPR_ATI(1) | \
327 FTSMC020_TPR_AT2(1) | \
328 FTSMC020_TPR_WTC(1) | \
329 FTSMC020_TPR_AHT(1) | \
330 FTSMC020_TPR_TRNA(1))
331 #endif /* CONFIG_FTSMC020 */
334 * FLASH and environment organization
336 /* use CFI framework */
337 #define CONFIG_SYS_FLASH_CFI
338 #define CONFIG_FLASH_CFI_DRIVER
340 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
341 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
345 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
346 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
347 #define PHYS_FLASH_1 0x80400000 /* BANK 1 */
348 #else /* !CONFIG_SKIP_LOWLEVEL_INIT */
349 #ifdef CONFIG_MEM_REMAP
350 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
352 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
353 #endif /* CONFIG_MEM_REMAP */
354 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
356 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
357 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
358 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
360 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
361 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
363 /* max number of memory banks */
365 * There are 4 banks supported for this Controller,
366 * but we have only 1 bank connected to flash on board
368 #define CONFIG_SYS_MAX_FLASH_BANKS 1
370 /* max number of sectors on one chip */
371 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2)
372 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
373 #define CONFIG_SYS_MAX_FLASH_SECT 128
376 #define CONFIG_ENV_IS_IN_FLASH
377 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
378 #define CONFIG_ENV_SIZE 8192
379 #define CONFIG_ENV_OVERWRITE
381 #endif /* __CONFIG_H */