2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch-ag101/ag101.h>
15 * CPU and Board Configuration Options
17 #define CONFIG_ADP_AG101P
19 #define CONFIG_USE_INTERRUPT
21 #define CONFIG_SKIP_LOWLEVEL_INIT
23 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
26 * Definitions related to passing arguments to kernel.
28 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
29 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
30 #define CONFIG_INITRD_TAG /* send initrd params */
32 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
33 #define CONFIG_MEM_REMAP
36 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
37 #define CONFIG_SYS_TEXT_BASE 0x00500000
39 #ifdef CONFIG_MEM_REMAP
40 #define CONFIG_SYS_TEXT_BASE 0x80000000
42 #define CONFIG_SYS_TEXT_BASE 0x00000000
49 #define CONFIG_SYS_CLK_FREQ 39062500
50 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
53 * Use Externel CLOCK or PCLK
55 #undef CONFIG_FTRTC010_EXTCLK
57 #ifndef CONFIG_FTRTC010_EXTCLK
58 #define CONFIG_FTRTC010_PCLK
61 #ifdef CONFIG_FTRTC010_EXTCLK
62 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
64 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
67 #define TIMER_LOAD_VAL 0xffffffff
72 #define CONFIG_RTC_FTRTC010
75 * Real Time Clock Divider
76 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
78 #define OSC_5MHZ (5*1000000)
79 #define OSC_CLK (4*OSC_5MHZ)
80 #define RTC_DIV_COUNT (0.5) /* Why?? */
83 * Serial console configuration
86 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
87 #define CONFIG_BAUDRATE 38400
88 #define CONFIG_CONS_INDEX 1
89 #define CONFIG_SYS_NS16550_SERIAL
90 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
91 #define CONFIG_SYS_NS16550_REG_SIZE -4
92 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
97 #define CONFIG_FTMAC100
101 * SD (MMC) controller
104 #define CONFIG_GENERIC_MMC
105 #define CONFIG_DOS_PARTITION
106 #define CONFIG_FTSDC010
107 #define CONFIG_FTSDC010_NUMBER 1
108 #define CONFIG_FTSDC010_SDIO
111 * Command line configuration.
113 #define CONFIG_CMD_DATE
116 * Miscellaneous configurable options
118 #define CONFIG_SYS_LONGHELP /* undef to save memory */
119 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
121 /* Print Buffer Size */
122 #define CONFIG_SYS_PBSIZE \
123 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
125 /* max number of command args */
126 #define CONFIG_SYS_MAXARGS 16
128 /* Boot Argument Buffer Size */
129 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
132 * Size of malloc() pool
134 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
135 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
138 * AHB Controller configuration
140 #define CONFIG_FTAHBC020S
142 #ifdef CONFIG_FTAHBC020S
143 #include <faraday/ftahbc020s.h>
145 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
146 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
149 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
150 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
153 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
154 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
155 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
161 #define CONFIG_FTWDT010_WATCHDOG
164 * PMU Power controller configuration
167 #define CONFIG_FTPMU010_POWER
169 #ifdef CONFIG_FTPMU010_POWER
170 #include <faraday/ftpmu010.h>
171 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
172 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
173 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
174 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
175 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
176 FTPMU010_SDRAMHTC_CKE_DCSR | \
177 FTPMU010_SDRAMHTC_DQM_DCSR | \
178 FTPMU010_SDRAMHTC_SDCLK_DCSR)
182 * SDRAM controller configuration
184 #define CONFIG_FTSDMC021
186 #ifdef CONFIG_FTSDMC021
187 #include <faraday/ftsdmc021.h>
189 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
190 FTSDMC021_TP1_TRP(1) | \
191 FTSDMC021_TP1_TRCD(1) | \
192 FTSDMC021_TP1_TRF(3) | \
193 FTSDMC021_TP1_TWR(1) | \
194 FTSDMC021_TP1_TCL(2))
196 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
197 FTSDMC021_TP2_INI_REFT(8) | \
198 FTSDMC021_TP2_REF_INTV(0x180))
201 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
202 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
205 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
206 FTSDMC021_CR1_DSZ(3) | \
207 FTSDMC021_CR1_MBW(2) | \
208 FTSDMC021_CR1_BNKSIZE(6))
210 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
211 FTSDMC021_CR2_IREF | \
214 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
215 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
216 CONFIG_SYS_FTSDMC021_BANK0_BASE)
218 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
219 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
220 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
221 CONFIG_SYS_FTSDMC021_BANK1_BASE)
225 * Physical Memory Map
227 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
228 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
230 #ifdef CONFIG_MEM_REMAP
231 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
233 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
237 #define PHYS_SDRAM_1 \
238 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
240 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
242 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
243 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
244 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
246 #ifdef CONFIG_MEM_REMAP
247 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
248 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
250 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
251 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
255 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
257 #ifdef CONFIG_MEM_REMAP
258 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
259 GENERATED_GBL_DATA_SIZE)
261 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
262 GENERATED_GBL_DATA_SIZE)
263 #endif /* CONFIG_MEM_REMAP */
266 * Load address and memory test area should agree with
267 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
269 #define CONFIG_SYS_LOAD_ADDR 0x300000
271 /* memtest works on 63 MB in DRAM */
272 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
273 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
276 * Static memory controller configuration
278 #define CONFIG_FTSMC020
280 #ifdef CONFIG_FTSMC020
281 #include <faraday/ftsmc020.h>
283 #define CONFIG_SYS_FTSMC020_CONFIGS { \
284 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
285 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
288 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
289 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
290 FTSMC020_BANK_SIZE_32M | \
291 FTSMC020_BANK_MBW_32)
293 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
294 FTSMC020_TPR_AST(1) | \
295 FTSMC020_TPR_CTW(1) | \
296 FTSMC020_TPR_ATI(1) | \
297 FTSMC020_TPR_AT2(1) | \
298 FTSMC020_TPR_WTC(1) | \
299 FTSMC020_TPR_AHT(1) | \
300 FTSMC020_TPR_TRNA(1))
304 * FLASH on ADP_AG101P is connected to BANK0
305 * Just disalbe the other BANK to avoid detection error.
307 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
308 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
309 FTSMC020_BANK_SIZE_32M | \
310 FTSMC020_BANK_MBW_32)
312 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
313 FTSMC020_TPR_CTW(3) | \
314 FTSMC020_TPR_ATI(0xf) | \
315 FTSMC020_TPR_AT2(3) | \
316 FTSMC020_TPR_WTC(3) | \
317 FTSMC020_TPR_AHT(3) | \
318 FTSMC020_TPR_TRNA(0xf))
320 #define FTSMC020_BANK1_CONFIG (0x00)
321 #define FTSMC020_BANK1_TIMING (0x00)
322 #endif /* CONFIG_FTSMC020 */
325 * FLASH and environment organization
327 /* use CFI framework */
328 #define CONFIG_SYS_FLASH_CFI
329 #define CONFIG_FLASH_CFI_DRIVER
331 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
332 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
333 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
337 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
338 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
339 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
341 #ifdef CONFIG_MEM_REMAP
342 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
344 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
346 #endif /* CONFIG_MEM_REMAP */
348 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
349 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
350 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
352 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
353 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
355 /* max number of memory banks */
357 * There are 4 banks supported for this Controller,
358 * but we have only 1 bank connected to flash on board
360 #define CONFIG_SYS_MAX_FLASH_BANKS 1
361 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
363 /* max number of sectors on one chip */
364 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
365 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
366 #define CONFIG_SYS_MAX_FLASH_SECT 512
369 #define CONFIG_ENV_IS_IN_FLASH
370 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
371 #define CONFIG_ENV_SIZE 8192
372 #define CONFIG_ENV_OVERWRITE
374 #endif /* __CONFIG_H */