git.sur5r.net Git - u-boot/blob - include/configs/adp-ag101p.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include <asm/arch-ag101/ag101.h>
  13
  14 /*
  15  * CPU and Board Configuration Options
  16  */
  17 #define CONFIG_ADP_AG101P
  18
  19 #define CONFIG_USE_INTERRUPT
  20
  21 #define CONFIG_SKIP_LOWLEVEL_INIT
  22
  23 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
  24
  25 /*
  26  * Definitions related to passing arguments to kernel.
  27  */
  28 #define CONFIG_CMDLINE_TAG                      /* send commandline to Kernel */
  29 #define CONFIG_SETUP_MEMORY_TAGS        /* send memory definition to kernel */
  30 #define CONFIG_INITRD_TAG                       /* send initrd params */
  31 #define CONFIG_NEEDS_MANUAL_RELOC
  32
  33 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  34 #define CONFIG_MEM_REMAP
  35 #endif
  36
  37 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  38 #define CONFIG_SYS_TEXT_BASE    0x00500000
  39 #else
  40 #ifdef CONFIG_MEM_REMAP
  41 #define CONFIG_SYS_TEXT_BASE    0x80000000
  42 #else
  43 #define CONFIG_SYS_TEXT_BASE    0x00000000
  44 #endif
  45 #endif
  46
  47 /*
  48  * Timer
  49  */
  50 #define CONFIG_SYS_CLK_FREQ     39062500
  51 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  52
  53 /*
  54  * Use Externel CLOCK or PCLK
  55  */
  56 #undef CONFIG_FTRTC010_EXTCLK
  57
  58 #ifndef CONFIG_FTRTC010_EXTCLK
  59 #define CONFIG_FTRTC010_PCLK
  60 #endif
  61
  62 #ifdef CONFIG_FTRTC010_EXTCLK
  63 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  64 #else
  65 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  66 #endif
  67
  68 #define TIMER_LOAD_VAL  0xffffffff
  69
  70 /*
  71  * Real Time Clock
  72  */
  73 #define CONFIG_RTC_FTRTC010
  74
  75 /*
  76  * Real Time Clock Divider
  77  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  78  */
  79 #define OSC_5MHZ                        (5*1000000)
  80 #define OSC_CLK                         (4*OSC_5MHZ)
  81 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  82
  83 /*
  84  * Serial console configuration
  85  */
  86
  87 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  88 #define CONFIG_BAUDRATE                 38400
  89 #define CONFIG_CONS_INDEX               1
  90 #define CONFIG_SYS_NS16550
  91 #define CONFIG_SYS_NS16550_SERIAL
  92 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  93 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  94 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  95
  96 /*
  97  * Ethernet
  98  */
  99 #define CONFIG_FTMAC100
 100
 101 #define CONFIG_BOOTDELAY        3
 102
 103 /*
 104  * SD (MMC) controller
 105  */
 106 #define CONFIG_MMC
 107 #define CONFIG_CMD_MMC
 108 #define CONFIG_GENERIC_MMC
 109 #define CONFIG_DOS_PARTITION
 110 #define CONFIG_FTSDC010
 111 #define CONFIG_FTSDC010_NUMBER          1
 112 #define CONFIG_FTSDC010_SDIO
 113 #define CONFIG_CMD_FAT
 114 #define CONFIG_CMD_EXT2
 115
 116 /*
 117  * Command line configuration.
 118  */
 119 #define CONFIG_CMD_CACHE
 120 #define CONFIG_CMD_DATE
 121 #define CONFIG_CMD_PING
 122
 123 /*
 124  * Miscellaneous configurable options
 125  */
 126 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 127 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 128
 129 /* Print Buffer Size */
 130 #define CONFIG_SYS_PBSIZE       \
 131         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 132
 133 /* max number of command args */
 134 #define CONFIG_SYS_MAXARGS      16
 135
 136 /* Boot Argument Buffer Size */
 137 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 138
 139 /*
 140  * Size of malloc() pool
 141  */
 142 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
 143 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 144
 145 /*
 146  * AHB Controller configuration
 147  */
 148 #define CONFIG_FTAHBC020S
 149
 150 #ifdef CONFIG_FTAHBC020S
 151 #include <faraday/ftahbc020s.h>
 152
 153 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
 154 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
 155
 156 /*
 157  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 158  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 159  * in C language.
 160  */
 161 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 162         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 163                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 164 #endif
 165
 166 /*
 167  * Watchdog
 168  */
 169 #define CONFIG_FTWDT010_WATCHDOG
 170
 171 /*
 172  * PMU Power controller configuration
 173  */
 174 #define CONFIG_PMU
 175 #define CONFIG_FTPMU010_POWER
 176
 177 #ifdef CONFIG_FTPMU010_POWER
 178 #include <faraday/ftpmu010.h>
 179 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 180 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 181                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 182                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 183                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 184                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 185                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 186                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 187 #endif
 188
 189 /*
 190  * SDRAM controller configuration
 191  */
 192 #define CONFIG_FTSDMC021
 193
 194 #ifdef CONFIG_FTSDMC021
 195 #include <faraday/ftsdmc021.h>
 196
 197 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 198                                          FTSDMC021_TP1_TRP(1)   |       \
 199                                          FTSDMC021_TP1_TRCD(1)  |       \
 200                                          FTSDMC021_TP1_TRF(3)   |       \
 201                                          FTSDMC021_TP1_TWR(1)   |       \
 202                                          FTSDMC021_TP1_TCL(2))
 203
 204 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 205                                          FTSDMC021_TP2_INI_REFT(8) |    \
 206                                          FTSDMC021_TP2_REF_INTV(0x180))
 207
 208 /*
 209  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 210  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 211  * C language.
 212  */
 213 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 214                                          FTSDMC021_CR1_DSZ(3)    |      \
 215                                          FTSDMC021_CR1_MBW(2)    |      \
 216                                          FTSDMC021_CR1_BNKSIZE(6))
 217
 218 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 219                                          FTSDMC021_CR2_IREF      |      \
 220                                          FTSDMC021_CR2_ISMR)
 221
 222 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 223 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 224                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 225
 226 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 227         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 228 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 229                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 230 #endif
 231
 232 /*
 233  * Physical Memory Map
 234  */
 235 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 236 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 237 #else
 238 #ifdef CONFIG_MEM_REMAP
 239 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 240 #else
 241 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 242 #endif
 243 #endif
 244
 245 #define PHYS_SDRAM_1 \
 246         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 247
 248 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
 249
 250 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 251 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 252 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 253 #else
 254 #ifdef CONFIG_MEM_REMAP
 255 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 256 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 257 #else
 258 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 259 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 260 #endif
 261 #endif
 262
 263 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 264
 265 #ifdef CONFIG_MEM_REMAP
 266 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 267                                         GENERATED_GBL_DATA_SIZE)
 268 #else
 269 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 270                                         GENERATED_GBL_DATA_SIZE)
 271 #endif /* CONFIG_MEM_REMAP */
 272
 273 /*
 274  * Load address and memory test area should agree with
 275  * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
 276  */
 277 #define CONFIG_SYS_LOAD_ADDR            0x300000
 278
 279 /* memtest works on 63 MB in DRAM */
 280 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 281 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 282
 283 /*
 284  * Static memory controller configuration
 285  */
 286 #define CONFIG_FTSMC020
 287
 288 #ifdef CONFIG_FTSMC020
 289 #include <faraday/ftsmc020.h>
 290
 291 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 292         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 293         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 294 }
 295
 296 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 297 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 298                                          FTSMC020_BANK_SIZE_32M |       \
 299                                          FTSMC020_BANK_MBW_32)
 300
 301 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 302                                          FTSMC020_TPR_AST(1)    |       \
 303                                          FTSMC020_TPR_CTW(1)    |       \
 304                                          FTSMC020_TPR_ATI(1)    |       \
 305                                          FTSMC020_TPR_AT2(1)    |       \
 306                                          FTSMC020_TPR_WTC(1)    |       \
 307                                          FTSMC020_TPR_AHT(1)    |       \
 308                                          FTSMC020_TPR_TRNA(1))
 309 #endif
 310
 311 /*
 312  * FLASH on ADP_AG101P is connected to BANK0
 313  * Just disalbe the other BANK to avoid detection error.
 314  */
 315 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 316                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 317                                  FTSMC020_BANK_SIZE_32M           |     \
 318                                  FTSMC020_BANK_MBW_32)
 319
 320 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 321                                  FTSMC020_TPR_CTW(3)   |        \
 322                                  FTSMC020_TPR_ATI(0xf) |        \
 323                                  FTSMC020_TPR_AT2(3)   |        \
 324                                  FTSMC020_TPR_WTC(3)   |        \
 325                                  FTSMC020_TPR_AHT(3)   |        \
 326                                  FTSMC020_TPR_TRNA(0xf))
 327
 328 #define FTSMC020_BANK1_CONFIG   (0x00)
 329 #define FTSMC020_BANK1_TIMING   (0x00)
 330 #endif /* CONFIG_FTSMC020 */
 331
 332 /*
 333  * FLASH and environment organization
 334  */
 335 /* use CFI framework */
 336 #define CONFIG_SYS_FLASH_CFI
 337 #define CONFIG_FLASH_CFI_DRIVER
 338
 339 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 340 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 341 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 342
 343 /* support JEDEC */
 344
 345 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 346 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 347 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 348 #else
 349 #ifdef CONFIG_MEM_REMAP
 350 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 351 #else
 352 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 353 #endif
 354 #endif  /* CONFIG_MEM_REMAP */
 355
 356 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 357 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 358 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 359
 360 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 361 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 362
 363 /* max number of memory banks */
 364 /*
 365  * There are 4 banks supported for this Controller,
 366  * but we have only 1 bank connected to flash on board
 367  */
 368 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 369 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 370
 371 /* max number of sectors on one chip */
 372 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 373 #define CONFIG_ENV_SECT_SIZE            CONFIG_FLASH_SECTOR_SIZE
 374 #define CONFIG_SYS_MAX_FLASH_SECT       512
 375
 376 /* environments */
 377 #define CONFIG_ENV_IS_IN_FLASH
 378 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + 0x140000)
 379 #define CONFIG_ENV_SIZE                 8192
 380 #define CONFIG_ENV_OVERWRITE
 381
 382 #endif  /* __CONFIG_H */