2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch-ag101/ag101.h>
15 * CPU and Board Configuration Options
17 #define CONFIG_ADP_AG101P
19 #define CONFIG_USE_INTERRUPT
21 #define CONFIG_SKIP_LOWLEVEL_INIT
23 #define CONFIG_CMDLINE_EDITING
25 #define CONFIG_SYS_ICACHE_OFF
26 #define CONFIG_SYS_DCACHE_OFF
28 #define CONFIG_BOOTP_SEND_HOSTNAME
29 #define CONFIG_BOOTP_SERVERIP
31 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
32 #define CONFIG_MEM_REMAP
35 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
36 #define CONFIG_SYS_TEXT_BASE 0x00500000
37 #ifdef CONFIG_OF_CONTROL
38 #undef CONFIG_OF_SEPARATE
39 #define CONFIG_OF_EMBED
42 #ifdef CONFIG_MEM_REMAP
43 #define CONFIG_SYS_TEXT_BASE 0x80000000
45 #define CONFIG_SYS_TEXT_BASE 0x00000000
52 #define CONFIG_SYS_CLK_FREQ 39062500
53 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
56 * Use Externel CLOCK or PCLK
58 #undef CONFIG_FTRTC010_EXTCLK
60 #ifndef CONFIG_FTRTC010_EXTCLK
61 #define CONFIG_FTRTC010_PCLK
64 #ifdef CONFIG_FTRTC010_EXTCLK
65 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
67 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
70 #define TIMER_LOAD_VAL 0xffffffff
75 #define CONFIG_RTC_FTRTC010
78 * Real Time Clock Divider
79 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
81 #define OSC_5MHZ (5*1000000)
82 #define OSC_CLK (4*OSC_5MHZ)
83 #define RTC_DIV_COUNT (0.5) /* Why?? */
86 * Serial console configuration
89 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
90 #define CONFIG_CONS_INDEX 1
91 #define CONFIG_SYS_NS16550_SERIAL
92 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
93 #ifndef CONFIG_DM_SERIAL
94 #define CONFIG_SYS_NS16550_REG_SIZE -4
96 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
101 #define CONFIG_FTSDC010
102 #define CONFIG_FTSDC010_NUMBER 1
103 #define CONFIG_FTSDC010_SDIO
106 * Miscellaneous configurable options
108 #define CONFIG_SYS_LONGHELP /* undef to save memory */
110 /* Print Buffer Size */
111 #define CONFIG_SYS_PBSIZE \
112 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
114 /* max number of command args */
115 #define CONFIG_SYS_MAXARGS 16
117 /* Boot Argument Buffer Size */
118 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
121 * Size of malloc() pool
123 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
124 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
127 * AHB Controller configuration
129 #define CONFIG_FTAHBC020S
131 #ifdef CONFIG_FTAHBC020S
132 #include <faraday/ftahbc020s.h>
134 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
135 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
138 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
139 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
142 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
143 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
144 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
150 #define CONFIG_FTWDT010_WATCHDOG
153 * PMU Power controller configuration
156 #define CONFIG_FTPMU010_POWER
158 #ifdef CONFIG_FTPMU010_POWER
159 #include <faraday/ftpmu010.h>
160 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
161 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
162 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
163 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
164 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
165 FTPMU010_SDRAMHTC_CKE_DCSR | \
166 FTPMU010_SDRAMHTC_DQM_DCSR | \
167 FTPMU010_SDRAMHTC_SDCLK_DCSR)
171 * SDRAM controller configuration
173 #define CONFIG_FTSDMC021
175 #ifdef CONFIG_FTSDMC021
176 #include <faraday/ftsdmc021.h>
178 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
179 FTSDMC021_TP1_TRP(1) | \
180 FTSDMC021_TP1_TRCD(1) | \
181 FTSDMC021_TP1_TRF(3) | \
182 FTSDMC021_TP1_TWR(1) | \
183 FTSDMC021_TP1_TCL(2))
185 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
186 FTSDMC021_TP2_INI_REFT(8) | \
187 FTSDMC021_TP2_REF_INTV(0x180))
190 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
191 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
194 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
195 FTSDMC021_CR1_DSZ(3) | \
196 FTSDMC021_CR1_MBW(2) | \
197 FTSDMC021_CR1_BNKSIZE(6))
199 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
200 FTSDMC021_CR2_IREF | \
203 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
204 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
205 CONFIG_SYS_FTSDMC021_BANK0_BASE)
207 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
208 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
209 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
210 CONFIG_SYS_FTSDMC021_BANK1_BASE)
214 * Physical Memory Map
216 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
217 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
219 #ifdef CONFIG_MEM_REMAP
220 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
222 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
226 #define PHYS_SDRAM_1 \
227 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
229 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
231 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
232 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
233 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
235 #ifdef CONFIG_MEM_REMAP
236 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
237 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
239 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
240 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
244 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
246 #ifdef CONFIG_MEM_REMAP
247 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
248 GENERATED_GBL_DATA_SIZE)
250 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
251 GENERATED_GBL_DATA_SIZE)
252 #endif /* CONFIG_MEM_REMAP */
255 * Load address and memory test area should agree with
256 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
258 #define CONFIG_SYS_LOAD_ADDR 0x300000
260 /* memtest works on 63 MB in DRAM */
261 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
262 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
265 * Static memory controller configuration
267 #define CONFIG_FTSMC020
269 #ifdef CONFIG_FTSMC020
270 #include <faraday/ftsmc020.h>
272 #define CONFIG_SYS_FTSMC020_CONFIGS { \
273 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
274 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
277 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
278 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
279 FTSMC020_BANK_SIZE_32M | \
280 FTSMC020_BANK_MBW_32)
282 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
283 FTSMC020_TPR_AST(1) | \
284 FTSMC020_TPR_CTW(1) | \
285 FTSMC020_TPR_ATI(1) | \
286 FTSMC020_TPR_AT2(1) | \
287 FTSMC020_TPR_WTC(1) | \
288 FTSMC020_TPR_AHT(1) | \
289 FTSMC020_TPR_TRNA(1))
293 * FLASH on ADP_AG101P is connected to BANK0
294 * Just disalbe the other BANK to avoid detection error.
296 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
297 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
298 FTSMC020_BANK_SIZE_32M | \
299 FTSMC020_BANK_MBW_32)
301 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
302 FTSMC020_TPR_CTW(3) | \
303 FTSMC020_TPR_ATI(0xf) | \
304 FTSMC020_TPR_AT2(3) | \
305 FTSMC020_TPR_WTC(3) | \
306 FTSMC020_TPR_AHT(3) | \
307 FTSMC020_TPR_TRNA(0xf))
309 #define FTSMC020_BANK1_CONFIG (0x00)
310 #define FTSMC020_BANK1_TIMING (0x00)
311 #endif /* CONFIG_FTSMC020 */
314 * FLASH and environment organization
316 /* use CFI framework */
317 #define CONFIG_SYS_FLASH_CFI
318 #define CONFIG_FLASH_CFI_DRIVER
320 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
321 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
322 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
326 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
327 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
328 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
330 #ifdef CONFIG_MEM_REMAP
331 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
333 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
335 #endif /* CONFIG_MEM_REMAP */
337 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
338 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
339 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
341 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
342 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
344 /* max number of memory banks */
346 * There are 4 banks supported for this Controller,
347 * but we have only 1 bank connected to flash on board
349 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
350 #define CONFIG_SYS_MAX_FLASH_BANKS 1
352 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
354 /* max number of sectors on one chip */
355 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
356 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
357 #define CONFIG_SYS_MAX_FLASH_SECT 512
360 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
361 #define CONFIG_ENV_SIZE 8192
362 #define CONFIG_ENV_OVERWRITE
365 * For booting Linux, the board info and command line data
366 * have to be in the first 16 MB of memory, since this is
367 * the maximum mapped by the Linux kernel during initialization.
370 /* Initial Memory map for Linux*/
371 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
372 /* Increase max gunzip size */
373 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
375 #endif /* __CONFIG_H */