2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/ag101.h>
15 * CPU and Board Configuration Options
17 #define CONFIG_ADP_AG101P
19 #define CONFIG_USE_INTERRUPT
21 #define CONFIG_SKIP_LOWLEVEL_INIT
23 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
24 #define CONFIG_MEM_REMAP
27 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
28 #define CONFIG_SYS_TEXT_BASE 0x03200000
30 #define CONFIG_SYS_TEXT_BASE 0x00000000
38 * According to the discussion in u-boot mailing list before,
39 * CONFIG_SYS_HZ at 1000 is mandatory.
41 #define CONFIG_SYS_HZ 1000
42 #define CONFIG_SYS_CLK_FREQ 39062500
43 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
46 * Use Externel CLOCK or PCLK
48 #undef CONFIG_FTRTC010_EXTCLK
50 #ifndef CONFIG_FTRTC010_EXTCLK
51 #define CONFIG_FTRTC010_PCLK
54 #ifdef CONFIG_FTRTC010_EXTCLK
55 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
57 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
60 #define TIMER_LOAD_VAL 0xffffffff
65 #define CONFIG_RTC_FTRTC010
68 * Real Time Clock Divider
69 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
71 #define OSC_5MHZ (5*1000000)
72 #define OSC_CLK (4*OSC_5MHZ)
73 #define RTC_DIV_COUNT (0.5) /* Why?? */
76 * Serial console configuration
79 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
80 #define CONFIG_BAUDRATE 38400
81 #define CONFIG_CONS_INDEX 1
82 #define CONFIG_SYS_NS16550
83 #define CONFIG_SYS_NS16550_SERIAL
84 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
85 #define CONFIG_SYS_NS16550_REG_SIZE -4
86 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
91 #define CONFIG_FTMAC100
93 #define CONFIG_BOOTDELAY 3
99 #define CONFIG_CMD_MMC
100 #define CONFIG_GENERIC_MMC
101 #define CONFIG_DOS_PARTITION
102 #define CONFIG_FTSDC010
103 #define CONFIG_FTSDC010_NUMBER 1
104 #define CONFIG_CMD_FAT
107 * Command line configuration.
109 #include <config_cmd_default.h>
111 #define CONFIG_CMD_CACHE
112 #define CONFIG_CMD_DATE
113 #define CONFIG_CMD_PING
116 * Miscellaneous configurable options
118 #define CONFIG_SYS_LONGHELP /* undef to save memory */
119 #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
120 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
122 /* Print Buffer Size */
123 #define CONFIG_SYS_PBSIZE \
124 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
126 /* max number of command args */
127 #define CONFIG_SYS_MAXARGS 16
129 /* Boot Argument Buffer Size */
130 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
133 * Size of malloc() pool
135 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
136 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
139 * size in bytes reserved for initial data
141 #define CONFIG_SYS_GBL_DATA_SIZE 128
144 * AHB Controller configuration
146 #define CONFIG_FTAHBC020S
148 #ifdef CONFIG_FTAHBC020S
149 #include <faraday/ftahbc020s.h>
151 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
152 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
155 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
156 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
159 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
160 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
161 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
167 #define CONFIG_FTWDT010_WATCHDOG
170 * PMU Power controller configuration
173 #define CONFIG_FTPMU010_POWER
175 #ifdef CONFIG_FTPMU010_POWER
176 #include <faraday/ftpmu010.h>
177 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
178 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
179 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
180 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
181 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
182 FTPMU010_SDRAMHTC_CKE_DCSR | \
183 FTPMU010_SDRAMHTC_DQM_DCSR | \
184 FTPMU010_SDRAMHTC_SDCLK_DCSR)
188 * SDRAM controller configuration
190 #define CONFIG_FTSDMC021
192 #ifdef CONFIG_FTSDMC021
193 #include <faraday/ftsdmc021.h>
195 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
196 FTSDMC021_TP1_TRP(1) | \
197 FTSDMC021_TP1_TRCD(1) | \
198 FTSDMC021_TP1_TRF(3) | \
199 FTSDMC021_TP1_TWR(1) | \
200 FTSDMC021_TP1_TCL(2))
202 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
203 FTSDMC021_TP2_INI_REFT(8) | \
204 FTSDMC021_TP2_REF_INTV(0x180))
207 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
208 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
211 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
212 FTSDMC021_CR1_DSZ(3) | \
213 FTSDMC021_CR1_MBW(2) | \
214 FTSDMC021_CR1_BNKSIZE(6))
216 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
217 FTSDMC021_CR2_IREF | \
220 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
221 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
222 CONFIG_SYS_FTSDMC021_BANK0_BASE)
227 * Physical Memory Map
229 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
230 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
231 #if defined(CONFIG_MEM_REMAP)
232 #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/
234 #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
235 #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */
238 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
239 #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
241 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
243 #ifdef CONFIG_MEM_REMAP
244 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
245 GENERATED_GBL_DATA_SIZE)
247 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
248 GENERATED_GBL_DATA_SIZE)
249 #endif /* CONFIG_MEM_REMAP */
252 * Load address and memory test area should agree with
253 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
255 #define CONFIG_SYS_LOAD_ADDR 0x300000
257 /* memtest works on 63 MB in DRAM */
258 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
259 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
262 * Static memory controller configuration
264 #define CONFIG_FTSMC020
266 #ifdef CONFIG_FTSMC020
267 #include <faraday/ftsmc020.h>
269 #define CONFIG_SYS_FTSMC020_CONFIGS { \
270 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
271 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
274 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
275 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
276 FTSMC020_BANK_SIZE_32M | \
277 FTSMC020_BANK_MBW_32)
279 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
280 FTSMC020_TPR_AST(1) | \
281 FTSMC020_TPR_CTW(1) | \
282 FTSMC020_TPR_ATI(1) | \
283 FTSMC020_TPR_AT2(1) | \
284 FTSMC020_TPR_WTC(1) | \
285 FTSMC020_TPR_AHT(1) | \
286 FTSMC020_TPR_TRNA(1))
290 * FLASH on ADP_AG101P is connected to BANK0
291 * Just disalbe the other BANK to avoid detection error.
293 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
294 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
295 FTSMC020_BANK_SIZE_32M | \
296 FTSMC020_BANK_MBW_32)
298 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
299 FTSMC020_TPR_CTW(3) | \
300 FTSMC020_TPR_ATI(0xf) | \
301 FTSMC020_TPR_AT2(3) | \
302 FTSMC020_TPR_WTC(3) | \
303 FTSMC020_TPR_AHT(3) | \
304 FTSMC020_TPR_TRNA(0xf))
306 #define FTSMC020_BANK1_CONFIG (0x00)
307 #define FTSMC020_BANK1_TIMING (0x00)
308 #endif /* CONFIG_FTSMC020 */
311 * FLASH and environment organization
313 /* use CFI framework */
314 #define CONFIG_SYS_FLASH_CFI
315 #define CONFIG_FLASH_CFI_DRIVER
317 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
318 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
322 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
323 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
324 #define PHYS_FLASH_1 0x80400000 /* BANK 1 */
325 #else /* !CONFIG_SKIP_LOWLEVEL_INIT */
326 #ifdef CONFIG_MEM_REMAP
327 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
329 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
330 #endif /* CONFIG_MEM_REMAP */
331 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
333 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
334 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
335 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
337 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
338 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
340 /* max number of memory banks */
342 * There are 4 banks supported for this Controller,
343 * but we have only 1 bank connected to flash on board
345 #define CONFIG_SYS_MAX_FLASH_BANKS 1
347 /* max number of sectors on one chip */
348 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2)
349 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
350 #define CONFIG_SYS_MAX_FLASH_SECT 128
353 #define CONFIG_ENV_IS_IN_FLASH
354 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
355 #define CONFIG_ENV_SIZE 8192
356 #define CONFIG_ENV_OVERWRITE
358 #endif /* __CONFIG_H */