2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch-ag101/ag101.h>
15 * CPU and Board Configuration Options
17 #define CONFIG_ADP_AG101P
19 #define CONFIG_USE_INTERRUPT
21 #define CONFIG_SKIP_LOWLEVEL_INIT
23 #define CONFIG_CMDLINE_EDITING
25 #define CONFIG_SYS_ICACHE_OFF
26 #define CONFIG_SYS_DCACHE_OFF
28 #define CONFIG_BOOTP_SEND_HOSTNAME
29 #define CONFIG_BOOTP_SERVERIP
31 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
32 #define CONFIG_MEM_REMAP
35 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
36 #define CONFIG_SYS_TEXT_BASE 0x00500000
37 #ifdef CONFIG_OF_CONTROL
38 #undef CONFIG_OF_SEPARATE
39 #define CONFIG_OF_EMBED
42 #ifdef CONFIG_MEM_REMAP
43 #define CONFIG_SYS_TEXT_BASE 0x80000000
45 #define CONFIG_SYS_TEXT_BASE 0x00000000
52 #define CONFIG_SYS_CLK_FREQ 39062500
53 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
56 * Use Externel CLOCK or PCLK
58 #undef CONFIG_FTRTC010_EXTCLK
60 #ifndef CONFIG_FTRTC010_EXTCLK
61 #define CONFIG_FTRTC010_PCLK
64 #ifdef CONFIG_FTRTC010_EXTCLK
65 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
67 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
70 #define TIMER_LOAD_VAL 0xffffffff
75 #define CONFIG_RTC_FTRTC010
78 * Real Time Clock Divider
79 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
81 #define OSC_5MHZ (5*1000000)
82 #define OSC_CLK (4*OSC_5MHZ)
83 #define RTC_DIV_COUNT (0.5) /* Why?? */
86 * Serial console configuration
89 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
90 #define CONFIG_CONS_INDEX 1
91 #define CONFIG_SYS_NS16550_SERIAL
92 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
93 #ifndef CONFIG_DM_SERIAL
94 #define CONFIG_SYS_NS16550_REG_SIZE -4
96 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
101 #define CONFIG_FTSDC010
102 #define CONFIG_FTSDC010_NUMBER 1
103 #define CONFIG_FTSDC010_SDIO
106 * Miscellaneous configurable options
108 #define CONFIG_SYS_LONGHELP /* undef to save memory */
111 * Size of malloc() pool
113 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
114 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
117 * AHB Controller configuration
119 #define CONFIG_FTAHBC020S
121 #ifdef CONFIG_FTAHBC020S
122 #include <faraday/ftahbc020s.h>
124 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
125 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
128 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
129 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
132 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
133 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
134 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
140 #define CONFIG_FTWDT010_WATCHDOG
143 * PMU Power controller configuration
146 #define CONFIG_FTPMU010_POWER
148 #ifdef CONFIG_FTPMU010_POWER
149 #include <faraday/ftpmu010.h>
150 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
151 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
152 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
153 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
154 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
155 FTPMU010_SDRAMHTC_CKE_DCSR | \
156 FTPMU010_SDRAMHTC_DQM_DCSR | \
157 FTPMU010_SDRAMHTC_SDCLK_DCSR)
161 * SDRAM controller configuration
163 #define CONFIG_FTSDMC021
165 #ifdef CONFIG_FTSDMC021
166 #include <faraday/ftsdmc021.h>
168 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
169 FTSDMC021_TP1_TRP(1) | \
170 FTSDMC021_TP1_TRCD(1) | \
171 FTSDMC021_TP1_TRF(3) | \
172 FTSDMC021_TP1_TWR(1) | \
173 FTSDMC021_TP1_TCL(2))
175 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
176 FTSDMC021_TP2_INI_REFT(8) | \
177 FTSDMC021_TP2_REF_INTV(0x180))
180 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
181 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
184 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
185 FTSDMC021_CR1_DSZ(3) | \
186 FTSDMC021_CR1_MBW(2) | \
187 FTSDMC021_CR1_BNKSIZE(6))
189 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
190 FTSDMC021_CR2_IREF | \
193 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
194 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
195 CONFIG_SYS_FTSDMC021_BANK0_BASE)
197 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
198 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
199 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
200 CONFIG_SYS_FTSDMC021_BANK1_BASE)
204 * Physical Memory Map
206 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
207 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
209 #ifdef CONFIG_MEM_REMAP
210 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
212 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
216 #define PHYS_SDRAM_1 \
217 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
219 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
221 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
222 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
223 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
225 #ifdef CONFIG_MEM_REMAP
226 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
227 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
229 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
230 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
234 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
236 #ifdef CONFIG_MEM_REMAP
237 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
238 GENERATED_GBL_DATA_SIZE)
240 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
241 GENERATED_GBL_DATA_SIZE)
242 #endif /* CONFIG_MEM_REMAP */
245 * Load address and memory test area should agree with
246 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
248 #define CONFIG_SYS_LOAD_ADDR 0x300000
250 /* memtest works on 63 MB in DRAM */
251 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
252 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
255 * Static memory controller configuration
257 #define CONFIG_FTSMC020
259 #ifdef CONFIG_FTSMC020
260 #include <faraday/ftsmc020.h>
262 #define CONFIG_SYS_FTSMC020_CONFIGS { \
263 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
264 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
267 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
268 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
269 FTSMC020_BANK_SIZE_32M | \
270 FTSMC020_BANK_MBW_32)
272 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
273 FTSMC020_TPR_AST(1) | \
274 FTSMC020_TPR_CTW(1) | \
275 FTSMC020_TPR_ATI(1) | \
276 FTSMC020_TPR_AT2(1) | \
277 FTSMC020_TPR_WTC(1) | \
278 FTSMC020_TPR_AHT(1) | \
279 FTSMC020_TPR_TRNA(1))
283 * FLASH on ADP_AG101P is connected to BANK0
284 * Just disalbe the other BANK to avoid detection error.
286 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
287 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
288 FTSMC020_BANK_SIZE_32M | \
289 FTSMC020_BANK_MBW_32)
291 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
292 FTSMC020_TPR_CTW(3) | \
293 FTSMC020_TPR_ATI(0xf) | \
294 FTSMC020_TPR_AT2(3) | \
295 FTSMC020_TPR_WTC(3) | \
296 FTSMC020_TPR_AHT(3) | \
297 FTSMC020_TPR_TRNA(0xf))
299 #define FTSMC020_BANK1_CONFIG (0x00)
300 #define FTSMC020_BANK1_TIMING (0x00)
301 #endif /* CONFIG_FTSMC020 */
304 * FLASH and environment organization
306 /* use CFI framework */
307 #define CONFIG_SYS_FLASH_CFI
308 #define CONFIG_FLASH_CFI_DRIVER
310 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
311 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
312 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
316 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
317 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
318 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
320 #ifdef CONFIG_MEM_REMAP
321 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
323 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
325 #endif /* CONFIG_MEM_REMAP */
327 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
328 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
329 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
331 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
332 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
334 /* max number of memory banks */
336 * There are 4 banks supported for this Controller,
337 * but we have only 1 bank connected to flash on board
339 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
340 #define CONFIG_SYS_MAX_FLASH_BANKS 1
342 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
344 /* max number of sectors on one chip */
345 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
346 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
347 #define CONFIG_SYS_MAX_FLASH_SECT 512
350 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
351 #define CONFIG_ENV_SIZE 8192
352 #define CONFIG_ENV_OVERWRITE
355 * For booting Linux, the board info and command line data
356 * have to be in the first 16 MB of memory, since this is
357 * the maximum mapped by the Linux kernel during initialization.
360 /* Initial Memory map for Linux*/
361 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
362 /* Increase max gunzip size */
363 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
365 #endif /* __CONFIG_H */