2 * Copyright (C) 2011 Andes Technology Corporation
3 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch-ag102/ag102.h>
14 * CPU and Board Configuration Options
16 #define CONFIG_ADP_AG102
18 #define CONFIG_USE_INTERRUPT
20 #define CONFIG_SKIP_LOWLEVEL_INIT
22 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
23 #define CONFIG_MEM_REMAP
26 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
27 #define CONFIG_SYS_TEXT_BASE 0x04200000
29 #define CONFIG_SYS_TEXT_BASE 0x00000000
35 #define CONFIG_SYS_CLK_FREQ (66000000 * 2)
36 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
39 * Use Externel CLOCK or PCLK
41 #undef CONFIG_FTRTC010_EXTCLK
43 #ifndef CONFIG_FTRTC010_EXTCLK
44 #define CONFIG_FTRTC010_PCLK
47 #ifdef CONFIG_FTRTC010_EXTCLK
48 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
50 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
53 #define TIMER_LOAD_VAL 0xffffffff
58 #define CONFIG_RTC_FTRTC010
61 * Real Time Clock Divider
62 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
64 #define OSC_5MHZ (5*1000000)
65 #define OSC_CLK (2*OSC_5MHZ)
66 #define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
69 * Serial console configuration
72 /* FTUART is a high speed NS 16C550A compatible UART */
73 #define CONFIG_BAUDRATE 38400
74 #define CONFIG_CONS_INDEX 1
75 #define CONFIG_SYS_NS16550
76 #define CONFIG_SYS_NS16550_SERIAL
77 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_01_BASE
78 #define CONFIG_SYS_NS16550_REG_SIZE -4
79 #define CONFIG_SYS_NS16550_CLK 33000000 /* AG102 */
84 #define CONFIG_PHY_MAX_ADDR 32 /* this comes from <linux/phy.h> */
85 #define CONFIG_SYS_DISCOVER_PHY
86 #define CONFIG_FTGMAC100
87 #define CONFIG_FTGMAC100_EGIGA
89 #define CONFIG_BOOTDELAY 3
95 #define CONFIG_CMD_MMC
96 #define CONFIG_GENERIC_MMC
97 #define CONFIG_DOS_PARTITION
98 #define CONFIG_FTSDC010
99 #define CONFIG_FTSDC010_NUMBER 1
100 #define CONFIG_FTSDC010_SDIO
101 #define CONFIG_CMD_FAT
102 #define CONFIG_CMD_EXT2
105 * Command line configuration.
107 #define CONFIG_CMD_CACHE
108 #define CONFIG_CMD_DATE
109 #define CONFIG_CMD_PING
110 #define CONFIG_CMD_IDE
111 #define CONFIG_CMD_FAT
112 #define CONFIG_CMD_ELF
119 #define CONFIG_FTPCI100
120 #define CONFIG_PCI_INDIRECT_BRIDGE
121 #define CONFIG_FTPCI100_MEM_BASE 0xa0000000
122 #define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */
123 #define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */
124 #define CONFIG_FTPCI100_MEM_BASE_SIZE1 0x50
126 #define CONFIG_PCI_MEM_BUS 0xa0000000
127 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
128 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* 256M */
130 #define CONFIG_PCI_IO_BUS 0x90000000
131 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
132 #define CONFIG_PCI_IO_SIZE 0x00100000 /* 1M */
137 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
138 #if defined(CONFIG_FTPCI100)
139 #define __io /* enable outl & inl */
140 #define CONFIG_CMD_USB
141 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5
142 #define CONFIG_USB_STORAGE
143 #define CONFIG_USB_EHCI
144 #define CONFIG_PCI_EHCI_DEVICE 0
145 #define CONFIG_USB_EHCI_PCI
146 #define CONFIG_PREBOOT "usb start;"
147 #endif /* #if defiend(CONFIG_FTPCI100) */
148 #endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
154 #define CONFIG_IDE_AHB
155 #define CONFIG_IDE_FTIDE020
157 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
158 #undef CONFIG_IDE_LED /* no led for ide supported */
159 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
160 #define CONFIG_IDE_PREINIT 1 /* preinit for ide */
162 /* max: 2 IDE busses */
163 #define CONFIG_SYS_IDE_MAXBUS 1 /* origin: 2 */
164 /* max: 2 drives per IDE bus */
165 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* origin: (MAXBUS * 2) */
167 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_FTIDE020S_BASE
168 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
169 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0000
171 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* for data I/O */
172 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* for normal regs access */
173 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* for alternate regs */
175 #define CONFIG_MAC_PARTITION
176 #define CONFIG_DOS_PARTITION
177 #define CONFIG_SUPPORT_VFAT
180 * Miscellaneous configurable options
182 #define CONFIG_SYS_LONGHELP /* undef to save memory */
183 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
185 /* Print Buffer Size */
186 #define CONFIG_SYS_PBSIZE \
187 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
189 /* max number of command args */
190 #define CONFIG_SYS_MAXARGS 16
192 /* Boot Argument Buffer Size */
193 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
196 * Size of malloc() pool
198 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
201 * AHB Controller configuration
203 #define CONFIG_FTAHBC020S
205 #ifdef CONFIG_FTAHBC020S
206 #include <faraday/ftahbc020s.h>
208 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
209 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
212 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
213 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
216 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
217 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
218 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
224 #define CONFIG_FTWDT010_WATCHDOG
227 * PCU Power Control Unit configuration
229 #define CONFIG_ANDES_PCU
231 #ifdef CONFIG_ANDES_PCU
232 #include <andestech/andes_pcu.h>
237 * DDR DRAM controller configuration
239 #define CONFIG_DWCDDR21MCTL
241 #ifdef CONFIG_DWCDDR21MCTL
242 #include <synopsys/dwcddr21mctl.h>
244 * 2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
245 * 1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
246 * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
247 * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
248 * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
250 #define CONFIG_SYS_DWCDDR21MCTL_CCR 0x00020004
251 #define CONFIG_SYS_DWCDDR21MCTL_CCR2 (DWCDDR21MCTL_CCR_DTT(0x1) | \
252 DWCDDR21MCTL_CCR_DFTLM(0x4) | \
253 DWCDDR21MCTL_CCR_HOSTEN(0x1))
255 /* 0x04: 0x000020d4 */
256 #define CONFIG_SYS_DWCDDR21MCTL_DCR 0x000020ca
258 /* 0x08: 0x0000000f */
259 #define CONFIG_SYS_DWCDDR21MCTL_IOCR 0x0000000f
261 /* 0x10: 0x00034812 */
262 #define CONFIG_SYS_DWCDDR21MCTL_DRR (DWCDDR21MCTL_DRR_TRFC(0x12) | \
263 DWCDDR21MCTL_DRR_TRFPRD(0x0348))
265 #define CONFIG_SYS_DWCDDR21MCTL_DLLCR0 DWCDDR21MCTL_DLLCR_PHASE(0x0)
267 /* 0x4c: 0x00000040 */
268 #define CONFIG_SYS_DWCDDR21MCTL_RSLR0 0x00000040
270 /* 0x5c: 0x000055CF */
271 #define CONFIG_SYS_DWCDDR21MCTL_RDGR0 0x000055cf
273 /* 0xa4: 0x00100000 */
274 #define CONFIG_SYS_DWCDDR21MCTL_DTAR (DWCDDR21MCTL_DTAR_DTBANK(0x0) | \
275 DWCDDR21MCTL_DTAR_DTROW(0x0100) | \
276 DWCDDR21MCTL_DTAR_DTCOL(0x0))
277 /* 0x1f0: 0x00000852 */
278 #define CONFIG_SYS_DWCDDR21MCTL_MR (DWCDDR21MCTL_MR_WR(0x4) | \
279 DWCDDR21MCTL_MR_CL(0x5) | \
280 DWCDDR21MCTL_MR_BL(0x2))
284 * Physical Memory Map
286 #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
287 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
288 #if defined(CONFIG_MEM_REMAP)
289 #define PHYS_SDRAM_0_AT_INIT 0x80000000 /* SDRAM Bank #1 before remap*/
291 #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
292 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
295 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
296 #define PHYS_SDRAM_0_SIZE 0x10000000 /* 256 MB */
298 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
300 #ifdef CONFIG_MEM_REMAP
301 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
302 GENERATED_GBL_DATA_SIZE)
304 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
305 GENERATED_GBL_DATA_SIZE)
306 #endif /* CONFIG_MEM_REMAP */
309 * Load address and memory test area should agree with
310 * board/faraday/a320/config.mk
311 * Be careful not to overwrite U-boot itself.
313 #define CONFIG_SYS_LOAD_ADDR 0x0CF00000
315 /* memtest works on 63 MB in DRAM */
316 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
317 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
320 * Static memory controller configuration
324 * FLASH and environment organization
326 #define CONFIG_SYS_NO_FLASH
329 * Env Storage Settings
331 #define CONFIG_ENV_IS_NOWHERE
332 #define CONFIG_ENV_SIZE 4096
334 #endif /* __CONFIG_H */