2 * (C) Copyright 2007 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * ADS5121 board configuration file
31 * Memory map for the ADS5121 board:
33 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
34 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
35 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
36 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
37 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
41 * High Level Configuration Options
43 #define CONFIG_E300 1 /* E300 Family */
44 #define CONFIG_MPC512X 1 /* MPC512X family */
48 #define CFG_MPC512X_CLKIN 66000000 /* in Hz */
50 #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
52 #define CFG_IMMR 0x80000000
54 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
55 #define CFG_MEMTEST_END 0x00400000
58 * DDR Setup - manually set all parameters as there's no SPD etc.
60 #define CFG_DDR_SIZE 256 /* MB */
61 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
62 #define CFG_SDRAM_BASE CFG_DDR_BASE
64 /* DDR Controller Configuration
67 * [31:31] MDDRC Soft Reset: Diabled
68 * [30:30] DRAM CKE pin: Enabled
69 * [29:29] DRAM CLK: Enabled
70 * [28:28] Command Mode: Enabled (For initialization only)
71 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
72 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
73 * [20:19] Read Test: DON'T USE
74 * [18:18] Self Refresh: Enabled
75 * [17:17] 16bit Mode: Disabled
76 * [16:13] Ready Delay: 2
77 * [12:12] Half DQS Delay: Disabled
78 * [11:11] Quarter DQS Delay: Disabled
79 * [10:08] Write Delay: 2
80 * [07:07] Early ODT: Disabled
81 * [06:06] On DIE Termination: Disabled
82 * [05:05] FIFO Overflow Clear: DON'T USE here
83 * [04:04] FIFO Underflow Clear: DON'T USE here
84 * [03:03] FIFO Overflow Pending: DON'T USE here
85 * [02:02] FIFO Underlfow Pending: DON'T USE here
86 * [01:01] FIFO Overlfow Enabled: Enabled
87 * [00:00] FIFO Underflow Enabled: Enabled
89 * [31:16] DRAM Refresh Time: 0 CSB clocks
90 * [15:8] DRAM Command Time: 0 CSB clocks
91 * [07:00] DRAM Precharge Time: 0 CSB clocks
102 * [22:19] DRAM tRTW1:
109 #define CFG_MDDRC_SYS_CFG 0xF8604A00
110 #define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
111 #define CFG_MDDRC_SYS_CFG_EN 0xF0000000
112 #define CFG_MDDRC_TIME_CFG0 0x00003D2E
113 #define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
114 #define CFG_MDDRC_TIME_CFG1 0x54EC1168
115 #define CFG_MDDRC_TIME_CFG2 0x35210864
117 #define CFG_MICRON_NOP 0x01380000
118 #define CFG_MICRON_PCHG_ALL 0x01100400
119 #define CFG_MICRON_EM2 0x01020000
120 #define CFG_MICRON_EM3 0x01030000
121 #define CFG_MICRON_EN_DLL 0x01010000
122 #define CFG_MICRON_RFSH 0x01080000
123 #define CFG_MICRON_INIT_DEV_OP 0x01000432
124 #define CFG_MICRON_OCD_DEFAULT 0x01010780
126 /* DDR Priority Manager Configuration */
127 #define CFG_MDDRCGRP_PM_CFG1 0x000777AA
128 #define CFG_MDDRCGRP_PM_CFG2 0x00000055
129 #define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000
130 #define CFG_MDDRCGRP_LUT0_MU 0x11111117
131 #define CFG_MDDRCGRP_LUT0_ML 0x7777777A
132 #define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE
133 #define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE
134 #define CFG_MDDRCGRP_LUT2_MU 0x44444444
135 #define CFG_MDDRCGRP_LUT2_ML 0x44444444
136 #define CFG_MDDRCGRP_LUT3_MU 0x55555555
137 #define CFG_MDDRCGRP_LUT3_ML 0x55555558
138 #define CFG_MDDRCGRP_LUT4_MU 0x11111111
139 #define CFG_MDDRCGRP_LUT4_ML 0x1111117C
140 #define CFG_MDDRCGRP_LUT0_AU 0x33333377
141 #define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE
142 #define CFG_MDDRCGRP_LUT1_AU 0x11111111
143 #define CFG_MDDRCGRP_LUT1_AL 0x11111111
144 #define CFG_MDDRCGRP_LUT2_AU 0x11111111
145 #define CFG_MDDRCGRP_LUT2_AL 0x11111111
146 #define CFG_MDDRCGRP_LUT3_AU 0x11111111
147 #define CFG_MDDRCGRP_LUT3_AL 0x11111111
148 #define CFG_MDDRCGRP_LUT4_AU 0x11111111
149 #define CFG_MDDRCGRP_LUT4_AL 0x11111111
152 * NOR FLASH on the Local Bus
154 #define CFG_FLASH_CFI /* use the Common Flash Interface */
155 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
156 #define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
157 #define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
158 #define CFG_FLASH_USE_BUFFER_WRITE
160 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
161 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
162 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
164 #undef CFG_FLASH_CHECKSUM
167 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
170 #define CFG_CPLD_BASE 0x82000000
171 #define CFG_CPLD_SIZE 0x00010000 /* 64 KB */
173 #define CFG_SRAM_BASE 0x30000000
174 #define CFG_SRAM_SIZE 0x00020000 /* 128 KB */
176 #define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
177 #define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
179 /* Use SRAM for initial stack */
180 #define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
181 #define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */
183 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
184 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
185 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
187 #define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */
188 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
189 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
194 #define CONFIG_CONS_INDEX 1
195 #undef CONFIG_SERIAL_SOFTWARE_FIFO
198 * Serial console configuration
200 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
201 #if CONFIG_PSC_CONSOLE != 3
202 #error CONFIG_PSC_CONSOLE must be 3
204 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
205 #define CFG_BAUDRATE_TABLE \
206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
208 #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
209 #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
210 #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
211 #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
213 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
214 /* Use the HUSH parser */
215 #define CFG_HUSH_PARSER
216 #ifdef CFG_HUSH_PARSER
217 #define CFG_PROMPT_HUSH_PS2 "> "
221 #define CONFIG_HARD_I2C /* I2C with hardware support */
222 #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
223 #define CONFIG_I2C_MULTI_BUS
224 #define CONFIG_I2C_CMD_TREE
225 #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
226 #define CFG_I2C_SLAVE 0x7F
228 #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
232 * EEPROM configuration
234 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
235 #define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
236 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
237 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
240 * Ethernet configuration
242 #define CONFIG_MPC512x_FEC 1
243 #define CONFIG_NET_MULTI
244 #define CONFIG_PHY_ADDR 0x1
245 #define CONFIG_MII 1 /* MII PHY management */
249 * Configure on-board RTC
251 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
252 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
258 #define CFG_ENV_IS_IN_FLASH 1
259 /* This has to be a multiple of the Flash sector size */
260 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
261 #define CFG_ENV_SIZE 0x2000
262 #define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
264 /* Address and size of Redundant Environment Sector */
265 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
266 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
268 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
269 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
271 #include <config_cmd_default.h>
273 #define CONFIG_CMD_ASKENV
274 #define CONFIG_CMD_DHCP
275 #define CONFIG_CMD_I2C
276 #define CONFIG_CMD_MII
277 #define CONFIG_CMD_NFS
278 #define CONFIG_CMD_PING
279 #define CONFIG_CMD_REGINFO
280 #define CONFIG_CMD_EEPROM
282 #if defined(CONFIG_PCI)
283 #define CONFIG_CMD_PCI
287 * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
288 * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
289 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
290 * to chapter 36 of the MPC5121e Reference Manual.
292 /* #define CONFIG_WATCHDOG */ /* enable watchdog */
293 #define CFG_WATCHDOG_VALUE 0xFFFF
296 * Miscellaneous configurable options
298 #define CFG_LONGHELP /* undef to save memory */
299 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
300 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
302 #ifdef CONFIG_CMD_KGDB
303 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
305 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
309 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
310 #define CFG_MAXARGS 16 /* max number of command args */
311 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
312 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
315 * For booting Linux, the board info and command line data
316 * have to be in the first 8 MB of memory, since this is
317 * the maximum mapped by the Linux kernel during initialization.
319 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
321 /* Cache Configuration */
322 #define CFG_DCACHE_SIZE 32768
323 #define CFG_CACHELINE_SIZE 32
324 #ifdef CONFIG_CMD_KGDB
325 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
328 #define CFG_HID0_INIT 0x000000000
329 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
330 #define CFG_HID2 HID2_HBE
333 * Internal Definitions
337 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
338 #define BOOTFLAG_WARM 0x02 /* Software reboot */
340 #ifdef CONFIG_CMD_KGDB
341 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
342 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
346 * Environment Configuration
348 #define CONFIG_TIMESTAMP
350 #define CONFIG_HOSTNAME ads5121
351 #define CONFIG_BOOTFILE ads5121/uImage
353 #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
355 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
356 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
358 #define CONFIG_BAUDRATE 115200
360 #define CONFIG_PREBOOT "echo;" \
361 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
364 #define CONFIG_EXTRA_ENV_SETTINGS \
365 "u-boot_addr_r=200000\0" \
366 "kernel_addr_r=200000\0" \
367 "fdt_addr_r=400000\0" \
368 "ramdisk_addr_r=500000\0" \
369 "u-boot_addr=FFF00000\0" \
370 "kernel_addr=FC000000\0" \
371 "fdt_addr=FC2C0000\0" \
372 "ramdisk_addr=FC300000\0" \
373 "ramdiskfile=ads5121/uRamdisk\0" \
374 "fdtfile=ads5121/ads5121.dtb\0" \
375 "u-boot=ads5121/u-boot.bin\0" \
377 "consdev=ttyPSC0\0" \
378 "nfsargs=setenv bootargs root=/dev/nfs rw " \
379 "nfsroot=${serverip}:${rootpath}\0" \
380 "ramargs=setenv bootargs root=/dev/ram rw\0" \
381 "addip=setenv bootargs ${bootargs} " \
382 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
383 ":${hostname}:${netdev}:off panic=1\0" \
384 "addtty=setenv bootargs ${bootargs} " \
385 "console=${consdev},${baudrate}\0" \
386 "flash_nfs=run nfsargs addip addtty;" \
387 "bootm ${kernel_addr_r} - ${fdt_addr}\0" \
388 "flash_self=run ramargs addip addtty;" \
389 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
390 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
391 "tftp ${fdt_addr_r} ${fdtfile};" \
392 "run nfsargs addip addtty;" \
393 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
394 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
395 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
396 "tftp ${fdt_addr} ${fdtfile};" \
397 "run ramargs addip addtty;" \
398 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr}\0"\
399 "load=tftp ${u-boot_addr} ${u-boot}\0" \
400 "update=protect off ${u-boot_addr} +${filesize};" \
401 "era ${u-boot_addr} +${filesize};" \
402 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
403 "upd=run load update\0" \
406 #define CONFIG_BOOTCOMMAND "run flash_self"
408 #define CONFIG_OF_LIBFDT 1
409 #define CONFIG_OF_BOARD_SETUP 1
411 #define OF_CPU "PowerPC,5121@0"
412 #define OF_SOC "soc@80000000"
413 #define OF_SOC_OLD "soc5121@80000000"
414 #define OF_TBCLK (bd->bi_busfreq / 4)
415 #define OF_STDOUT_PATH "/soc@80000000/serial@11300"
417 #endif /* __CONFIG_H */