1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2016 Timesys Corporation
4 * Copyright (C) 2016 Advantech Corporation
5 * Copyright (C) 2012 Freescale Semiconductor, Inc.
8 #ifndef __ADVANTECH_DMSBA16_CONFIG_H
9 #define __ADVANTECH_DMSBA16_CONFIG_H
11 #include <asm/arch/imx-regs.h>
12 #include <asm/mach-imx/gpio.h>
14 #define CONFIG_BOARD_NAME "Advantech DMS-BA16"
16 #define CONFIG_MXC_UART_BASE UART4_BASE
17 #define CONSOLE_DEV "ttymxc3"
18 #define CONFIG_EXTRA_BOOTARGS "panic=10"
20 #define CONFIG_BOOT_DIR ""
21 #define CONFIG_LOADCMD "fatload"
22 #define CONFIG_RFSPART "2"
24 #define CONFIG_SUPPORT_EMMC_BOOT
26 #include "mx6_common.h"
27 #include <linux/sizes.h>
29 #define CONFIG_CMDLINE_TAG
30 #define CONFIG_SETUP_MEMORY_TAGS
31 #define CONFIG_INITRD_TAG
32 #define CONFIG_REVISION_TAG
33 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
35 #define CONFIG_MXC_UART
37 #define CONFIG_MXC_OCOTP
40 #define CONFIG_SYS_SATA_MAX_DEVICE 1
41 #define CONFIG_DWC_AHSATA_PORT_ID 0
42 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
46 #define CONFIG_FSL_USDHC
47 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
50 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
51 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
52 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
53 #define CONFIG_MXC_USB_FLAGS 0
55 #define CONFIG_USBD_HS
57 /* Networking Configs */
58 #define CONFIG_FEC_MXC
60 #define IMX_FEC_BASE ENET_BASE_ADDR
61 #define CONFIG_FEC_XCV_TYPE RGMII
62 #define CONFIG_ETHPRIME "FEC"
63 #define CONFIG_FEC_MXC_PHYADDR 4
64 #define CONFIG_PHY_ATHEROS
68 #define CONFIG_SF_DEFAULT_BUS 0
69 #define CONFIG_SF_DEFAULT_CS 0
70 #define CONFIG_SF_DEFAULT_SPEED 20000000
71 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
74 /* allow to overwrite serial and ethaddr */
75 #define CONFIG_ENV_OVERWRITE
77 #define CONFIG_LOADADDR 0x12000000
79 #define CONFIG_EXTRA_ENV_SETTINGS \
81 "image=" CONFIG_BOOT_DIR "/uImage\0" \
82 "uboot=u-boot.imx\0" \
83 "fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \
84 "fdt_addr=0x18000000\0" \
87 "console=" CONSOLE_DEV "\0" \
88 "fdt_high=0xffffffff\0" \
89 "initrd_high=0xffffffff\0" \
93 "loadcmd=" CONFIG_LOADCMD "\0" \
94 "rfspart=" CONFIG_RFSPART "\0" \
95 "update_sd_firmware=" \
96 "if test ${ip_dyn} = yes; then " \
97 "setenv get_cmd dhcp; " \
99 "setenv get_cmd tftp; " \
101 "if mmc dev ${mmcdev}; then " \
102 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
103 "setexpr fw_sz ${filesize} / 0x200; " \
104 "setexpr fw_sz ${fw_sz} + 1; " \
105 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
109 "if tftp $loadaddr $uboot; then " \
111 "sf erase 0 0xC0000; " \
112 "sf write $loadaddr 0x400 $filesize; " \
113 "echo 'U-Boot upgraded. Please reset'; " \
115 "setargs=setenv bootargs console=${console},${baudrate} " \
116 "root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \
118 "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
119 "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
122 "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
123 "loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
125 "if run loadbootscript; then " \
128 "if run loadimage; then " \
132 "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \
134 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
135 "if run loadfdt; then " \
136 "bootm ${loadaddr} - ${fdt_addr}; " \
138 "if test ${boot_fdt} = try; then " \
141 "echo WARN: Cannot load the DT; " \
147 "netargs=setenv bootargs console=${console},${baudrate} " \
149 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
150 "netboot=echo Booting from net ...; " \
152 "if test ${ip_dyn} = yes; then " \
153 "setenv get_cmd dhcp; " \
155 "setenv get_cmd tftp; " \
157 "${get_cmd} ${image}; " \
158 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
159 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
160 "bootm ${loadaddr} - ${fdt_addr}; " \
162 "if test ${boot_fdt} = try; then " \
165 "echo WARN: Cannot load the DT; " \
172 #define CONFIG_BOOTCOMMAND \
175 "setenv devnum 0; " \
176 "setenv rootdev sda${rfspart}; " \
180 "setenv rootdev mmcblk0p${rfspart}; " \
182 "setenv devnum ${sddev}; " \
183 "if mmc dev ${devnum}; then " \
187 "setenv devnum ${emmcdev}; " \
188 "setenv rootdev mmcblk${emmcdev}p${rfspart}; " \
189 "if mmc dev ${devnum}; then " \
195 #define CONFIG_ARP_TIMEOUT 200UL
197 /* Miscellaneous configurable options */
199 #define CONFIG_SYS_MEMTEST_START 0x10000000
200 #define CONFIG_SYS_MEMTEST_END 0x10010000
201 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
203 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
205 /* Physical Memory Map */
206 #define CONFIG_NR_DRAM_BANKS 1
207 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
209 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
210 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
211 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
213 #define CONFIG_SYS_INIT_SP_OFFSET \
214 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
215 #define CONFIG_SYS_INIT_SP_ADDR \
216 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
218 /* FLASH and environment organization */
220 #define CONFIG_ENV_SIZE (8 * 1024)
221 #define CONFIG_ENV_OFFSET (768 * 1024)
222 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
223 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
224 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
225 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
226 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
228 #ifndef CONFIG_SYS_DCACHE_OFF
231 #define CONFIG_SYS_FSL_USDHC_NUM 3
235 #define CONFIG_VIDEO_IPUV3
236 #define CONFIG_VIDEO_BMP_RLE8
237 #define CONFIG_SPLASH_SCREEN
238 #define CONFIG_SPLASH_SCREEN_ALIGN
239 #define CONFIG_BMP_16BPP
240 #define CONFIG_VIDEO_LOGO
241 #define CONFIG_VIDEO_BMP_LOGO
242 #define CONFIG_IMX_HDMI
243 #define CONFIG_IMX_VIDEO_SKIP
246 #define CONFIG_PWM_IMX
247 #define CONFIG_IMX6_PWM_PER_CLK 66000000
249 #ifdef CONFIG_CMD_PCI
250 #define CONFIG_PCI_SCAN_SHOW
251 #define CONFIG_PCIE_IMX
252 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
253 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
257 #define CONFIG_SYS_I2C
258 #define CONFIG_SYS_I2C_MXC
259 #define CONFIG_SYS_I2C_SPEED 100000
260 #define CONFIG_SYS_I2C_MXC_I2C1
261 #define CONFIG_SYS_I2C_MXC_I2C2
262 #define CONFIG_SYS_I2C_MXC_I2C3
264 #endif /* __ADVANTECH_DMSBA16_CONFIG_H */