2 * am3517_evm.h - Default configuration for AM3517 EVM board.
4 * Author: Vaibhav Hiremath <hvaibhav@ti.com>
6 * Based on omap3_evm_config.h
8 * Copyright (C) 2010 Texas Instruments Incorporated
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * High Level Configuration Options
31 #define CONFIG_OMAP 1 /* in a TI OMAP core */
32 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
33 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
35 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
37 #include <asm/arch/cpu.h> /* get chip and board defs */
38 #include <asm/arch/omap3.h>
41 * Display CPU and Board information
43 #define CONFIG_DISPLAY_CPUINFO 1
44 #define CONFIG_DISPLAY_BOARDINFO 1
47 #define V_OSCK 26000000 /* Clock output from T2 */
48 #define V_SCLK (V_OSCK >> 1)
50 #define CONFIG_MISC_INIT_R
52 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
53 #define CONFIG_SETUP_MEMORY_TAGS 1
54 #define CONFIG_INITRD_TAG 1
55 #define CONFIG_REVISION_TAG 1
58 * Size of malloc() pool
60 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
61 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
65 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
72 * NS16550 Configuration
74 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
76 #define CONFIG_SYS_NS16550
77 #define CONFIG_SYS_NS16550_SERIAL
78 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
79 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
82 * select serial console configuration
84 #define CONFIG_CONS_INDEX 3
85 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
86 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */
88 /* allow to overwrite serial and ethaddr */
89 #define CONFIG_ENV_OVERWRITE
90 #define CONFIG_BAUDRATE 115200
91 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
94 #define CONFIG_GENERIC_MMC 1
95 #define CONFIG_OMAP_HSMMC 1
96 #define CONFIG_DOS_PARTITION 1
100 * Enable CONFIG_MUSB_HOST for Host functionalities MSC, keyboard
101 * Enable CONFIG_MUSB_GADGET for Device functionalities.
103 #define CONFIG_USB_MUSB_AM35X
104 #define CONFIG_MUSB_HOST
105 #define CONFIG_MUSB_PIO_ONLY
107 #ifdef CONFIG_USB_MUSB_AM35X
109 #ifdef CONFIG_MUSB_HOST
110 #define CONFIG_CMD_USB
112 #define CONFIG_USB_STORAGE
113 #define CONGIG_CMD_STORAGE
114 #define CONFIG_CMD_FAT
116 #ifdef CONFIG_USB_KEYBOARD
117 #define CONFIG_SYS_USB_EVENT_POLL
118 #define CONFIG_PREBOOT "usb start"
119 #endif /* CONFIG_USB_KEYBOARD */
121 #endif /* CONFIG_MUSB_HOST */
123 #ifdef CONFIG_MUSB_GADGET
124 #define CONFIG_USB_GADGET_DUALSPEED
125 #define CONFIG_USB_ETHER
126 #define CONFIG_USB_ETH_RNDIS
127 #endif /* CONFIG_MUSB_GADGET */
129 #endif /* CONFIG_USB_MUSB_AM35X */
131 /* commands to include */
132 #include <config_cmd_default.h>
134 #define CONFIG_CMD_EXT2 /* EXT2 Support */
135 #define CONFIG_CMD_FAT /* FAT support */
136 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
138 #define CONFIG_CMD_I2C /* I2C serial bus support */
139 #define CONFIG_CMD_MMC /* MMC support */
140 #define CONFIG_CMD_NAND /* NAND support */
141 #define CONFIG_CMD_DHCP
142 #undef CONFIG_CMD_PING
144 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
145 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
146 #undef CONFIG_CMD_IMI /* iminfo */
147 #undef CONFIG_CMD_IMLS /* List all found images */
149 #define CONFIG_SYS_NO_FLASH
150 #define CONFIG_HARD_I2C 1
151 #define CONFIG_SYS_I2C_SPEED 100000
152 #define CONFIG_SYS_I2C_SLAVE 1
153 #define CONFIG_SYS_I2C_BUS 0
154 #define CONFIG_SYS_I2C_BUS_SELECT 1
155 #define CONFIG_DRIVER_OMAP34XX_I2C 1
157 #undef CONFIG_CMD_NET
158 #undef CONFIG_CMD_NFS
162 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
164 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
168 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
170 #define CONFIG_JFFS2_NAND
171 /* nand device jffs2 lives on */
172 #define CONFIG_JFFS2_DEV "nand0"
173 /* start of jffs2 partition */
174 #define CONFIG_JFFS2_PART_OFFSET 0x680000
175 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
177 /* Environment information */
178 #define CONFIG_BOOTDELAY 10
180 #define CONFIG_BOOTFILE "uImage"
182 #define CONFIG_EXTRA_ENV_SETTINGS \
183 "loadaddr=0x82000000\0" \
184 "console=ttyO2,115200n8\0" \
186 "mmcargs=setenv bootargs console=${console} " \
187 "root=/dev/mmcblk0p2 rw rootwait\0" \
188 "nandargs=setenv bootargs console=${console} " \
189 "root=/dev/mtdblock4 rw " \
190 "rootfstype=jffs2\0" \
191 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
192 "bootscript=echo Running bootscript from mmc ...; " \
193 "source ${loadaddr}\0" \
194 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
195 "mmcboot=echo Booting from mmc ...; " \
197 "bootm ${loadaddr}\0" \
198 "nandboot=echo Booting from nand ...; " \
200 "nand read ${loadaddr} 280000 400000; " \
201 "bootm ${loadaddr}\0" \
203 #define CONFIG_BOOTCOMMAND \
204 "mmc dev ${mmcdev}; if mmc rescan; then " \
205 "if run loadbootscript; then " \
208 "if run loaduimage; then " \
210 "else run nandboot; " \
213 "else run nandboot; fi"
215 #define CONFIG_AUTO_COMPLETE 1
217 * Miscellaneous configurable options
219 #define V_PROMPT "AM3517_EVM # "
221 #define CONFIG_SYS_LONGHELP /* undef to save memory */
222 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
223 #define CONFIG_SYS_PROMPT V_PROMPT
224 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
225 /* Print Buffer Size */
226 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
227 sizeof(CONFIG_SYS_PROMPT) + 16)
228 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
230 /* Boot Argument Buffer Size */
231 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
232 /* memtest works on */
233 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
234 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
235 0x01F00000) /* 31MB */
237 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
241 * AM3517 has 12 GP timers, they can be driven by the system clock
242 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
243 * This rate is divided by a local divisor.
245 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
246 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
247 #define CONFIG_SYS_HZ 1000
249 /*-----------------------------------------------------------------------
250 * Physical Memory Map
252 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
253 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
254 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
256 /*-----------------------------------------------------------------------
257 * FLASH and environment organization
260 /* **** PISMO SUPPORT *** */
262 /* Configure the PISMO */
263 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
264 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
266 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
268 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
269 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
271 #if defined(CONFIG_CMD_NAND)
272 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
275 /* Monitor at start of flash */
276 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
278 #define CONFIG_NAND_OMAP_GPMC
279 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
280 #define CONFIG_ENV_IS_IN_NAND 1
281 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
283 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
284 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
285 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
287 /*-----------------------------------------------------------------------
288 * CFI FLASH driver setup
290 /* timeout values are in ticks */
291 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
292 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
294 /* Flash banks JFFS2 should use */
295 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
296 CONFIG_SYS_MAX_NAND_DEVICE)
297 #define CONFIG_SYS_JFFS2_MEM_NAND
298 /* use flash_info[2] */
299 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
300 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
302 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
303 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
304 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
305 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
306 CONFIG_SYS_INIT_RAM_SIZE - \
307 GENERATED_GBL_DATA_SIZE)
309 /* Defines for SPL */
311 #define CONFIG_SPL_FRAMEWORK
312 #define CONFIG_SPL_BOARD_INIT
313 #define CONFIG_SPL_NAND_SIMPLE
314 #define CONFIG_SPL_TEXT_BASE 0x40200800
315 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
316 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
318 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
319 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
321 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
322 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
323 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
324 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
326 #define CONFIG_SPL_LIBCOMMON_SUPPORT
327 #define CONFIG_SPL_LIBDISK_SUPPORT
328 #define CONFIG_SPL_I2C_SUPPORT
329 #define CONFIG_SPL_LIBGENERIC_SUPPORT
330 #define CONFIG_SPL_MMC_SUPPORT
331 #define CONFIG_SPL_FAT_SUPPORT
332 #define CONFIG_SPL_SERIAL_SUPPORT
333 #define CONFIG_SPL_NAND_SUPPORT
334 #define CONFIG_SPL_NAND_BASE
335 #define CONFIG_SPL_NAND_DRIVERS
336 #define CONFIG_SPL_NAND_ECC
337 #define CONFIG_SPL_POWER_SUPPORT
338 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
340 /* NAND boot config */
341 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
342 #define CONFIG_SYS_NAND_PAGE_COUNT 64
343 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
344 #define CONFIG_SYS_NAND_OOBSIZE 64
345 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
346 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
347 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
349 #define CONFIG_SYS_NAND_ECCSIZE 512
350 #define CONFIG_SYS_NAND_ECCBYTES 3
351 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
352 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
355 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
356 * 64 bytes before this address should be set aside for u-boot.img's
357 * header. That is 0x800FFFC0--0x80100000 should not be used for any
360 #define CONFIG_SYS_TEXT_BASE 0x80100000
361 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
362 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
364 #endif /* __CONFIG_H */