2 * Configuation settings for the Renesas Solutions AP-325RXA board
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #define CONFIG_CPU_SH7723 1
15 #define CONFIG_DISPLAY_BOARDINFO
16 #undef CONFIG_SHOW_BOOT_PROGRESS
19 #define AP325RXA_SDRAM_BASE (0x88000000)
20 #define AP325RXA_FLASH_BASE_1 (0xA0000000)
21 #define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
23 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
25 /* undef to save memory */
26 #define CONFIG_SYS_LONGHELP
27 /* Monitor Command Prompt */
28 /* Buffer size for Console output */
29 #define CONFIG_SYS_PBSIZE 256
30 /* List of legal baudrate settings for this board */
31 #define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
34 #define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
35 #define CONFIG_CONS_SCIF5 1
37 /* Suppress display of console information at boot */
39 #define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
40 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
42 /* Enable alternate, more extensive, memory test */
43 #undef CONFIG_SYS_ALT_MEMTEST
44 /* Scratch address used by the alternate memory test */
45 #undef CONFIG_SYS_MEMTEST_SCRATCH
47 /* Enable temporary baudrate change while serial download */
48 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
50 #define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
51 /* maybe more, but if so u-boot doesn't know about it... */
52 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
53 /* default load address for scripts ?!? */
54 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
56 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
57 #define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
59 #define CONFIG_SYS_MONITOR_LEN (128 * 1024)
60 /* Size of DRAM reserved for malloc() use */
61 #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
62 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
65 #define CONFIG_FLASH_CFI_DRIVER 1
66 #define CONFIG_SYS_FLASH_CFI
67 #undef CONFIG_SYS_FLASH_QUIET_TEST
68 /* print 'E' for empty sector on flinfo */
69 #define CONFIG_SYS_FLASH_EMPTY_INFO
70 /* Physical start address of Flash memory */
71 #define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
72 /* Max number of sectors on each Flash chip */
73 #define CONFIG_SYS_MAX_FLASH_SECT 512
78 #define CONFIG_IDE_RESET 1
79 #define CONFIG_SYS_PIO_MODE 1
80 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
81 #define CONFIG_SYS_IDE_MAXDEVICE 1
82 #define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
83 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
84 #define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
85 #define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
86 #define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
87 #define CONFIG_IDE_SWAP_IO
89 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
90 #define CONFIG_SYS_MAX_FLASH_BANKS 1
91 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
93 /* Timeout for Flash erase operations (in ms) */
94 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
95 /* Timeout for Flash write operations (in ms) */
96 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
97 /* Timeout for Flash set sector lock bit operations (in ms) */
98 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
99 /* Timeout for Flash clear lock bit operations (in ms) */
100 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
103 * Use hardware flash sectors protection instead
104 * of U-Boot software protection
106 #undef CONFIG_SYS_FLASH_PROTECTION
107 #undef CONFIG_SYS_DIRECT_FLASH_TFTP
110 #define CONFIG_ENV_OVERWRITE 1
111 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
112 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
113 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
114 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
115 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
116 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
119 #define CONFIG_SYS_CLK_FREQ 33333333
120 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
121 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
122 #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
124 #endif /* __AP325RXA_H */